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[Qemu-devel] [PATCH] Fix extlh instruction on Alpha

From: Vince Weaver
Subject: [Qemu-devel] [PATCH] Fix extlh instruction on Alpha
Date: Thu, 17 Sep 2009 15:28:52 -0400 (EDT)

The extlh instruction on Alpha currently doesn't work properly.
It's a combination of a cut/paste bug (16 where it should be 32) as well 
as a "shift by 64" bug.

This improves on an earlier patch that used labels, conditional jumps, 
and local variables.  Thanks go especially to Aurelien Jarno and Andreas 
Schwab who have a much better eye for bit-wise TCG optimization than I do.


Signed-off-by: Vince Weaver <address@hidden>

diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 9d2bc45..9e7e9b2 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -524,14 +524,15 @@ static inline void gen_ext_h(void(*tcg_gen_ext_i64)(TCGv 
t0, TCGv t1),
                 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]);
         } else {
-            TCGv tmp1, tmp2;
+            TCGv tmp1;
             tmp1 = tcg_temp_new();
             tcg_gen_andi_i64(tmp1, cpu_ir[rb], 7);
             tcg_gen_shli_i64(tmp1, tmp1, 3);
-            tmp2 = tcg_const_i64(64);
-            tcg_gen_sub_i64(tmp1, tmp2, tmp1);
-            tcg_temp_free(tmp2);
+            tcg_gen_neg_i64(tmp1, tmp1);
+            tcg_gen_andi_i64(tmp1, tmp1, 0x3f);
             tcg_gen_shl_i64(cpu_ir[rc], cpu_ir[ra], tmp1);
         if (tcg_gen_ext_i64)
@@ -1316,7 +1317,7 @@ static inline int translate_one(DisasContext *ctx, 
uint32_t insn)
         case 0x6A:
             /* EXTLH */
-            gen_ext_h(&tcg_gen_ext16u_i64, ra, rb, rc, islit, lit);
+            gen_ext_h(&tcg_gen_ext32u_i64, ra, rb, rc, islit, lit);
         case 0x72:
             /* MSKQH */

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