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[Qemu-devel] Re: [PATCH 14/20] pci: remove unused constants.


From: Michael S. Tsirkin
Subject: [Qemu-devel] Re: [PATCH 14/20] pci: remove unused constants.
Date: Thu, 12 Nov 2009 12:33:48 +0200
User-agent: Mutt/1.5.19 (2009-01-05)

On Thu, Nov 12, 2009 at 02:58:42PM +0900, Isaku Yamahata wrote:
> This patch removes unused constants committed by
> fb23162885f7fd8cf7334bed22c25ac32c7d8b9d.
> 
> Signed-off-by: Isaku Yamahata <address@hidden>

Acked-by: Michael S. Tsirkin <address@hidden>

> ---
>  hw/pci.h |    9 ---------
>  1 files changed, 0 insertions(+), 9 deletions(-)
> 
> diff --git a/hw/pci.h b/hw/pci.h
> index 988d2c0..72a476e 100644
> --- a/hw/pci.h
> +++ b/hw/pci.h
> @@ -101,14 +101,6 @@ typedef struct PCIIORegion {
>  #define  PCI_COMMAND_IO              0x1     /* Enable response in I/O space 
> */
>  #define  PCI_COMMAND_MEMORY  0x2     /* Enable response in Memory space */
>  #define  PCI_COMMAND_MASTER  0x4     /* Enable bus master */
> -#define  PCI_COMMAND_SPECIAL 0x8     /* Enable response to special cycles */
> -#define  PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
> -#define  PCI_COMMAND_VGA_PALETTE 0x20        /* Enable palette snooping */
> -#define  PCI_COMMAND_PARITY  0x40    /* Enable parity checking */
> -#define  PCI_COMMAND_WAIT    0x80    /* Enable address/data stepping */
> -#define  PCI_COMMAND_SERR    0x100   /* Enable SERR */
> -#define  PCI_COMMAND_FAST_BACK       0x200   /* Enable back-to-back writes */
> -#define  PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
>  #define PCI_STATUS              0x06    /* 16 bits */
>  #define PCI_REVISION_ID         0x08    /* 8 bits  */
>  #define PCI_CLASS_PROG               0x09    /* Reg. Level Programming 
> Interface */
> @@ -128,7 +120,6 @@ typedef struct PCIIORegion {
>  #define PCI_PRIMARY_BUS              0x18    /* Primary bus number */
>  #define PCI_SECONDARY_BUS    0x19    /* Secondary bus number */
>  #define PCI_SUBORDINATE_BUS  0x1a    /* Highest bus number behind the bridge 
> */
> -#define PCI_SEC_LATENCY_TIMER   0x1b    /* Latency timer for secondary 
> interface */
>  #define PCI_IO_BASE             0x1c    /* I/O range behind the bridge */
>  #define PCI_IO_LIMIT            0x1d
>  #define  PCI_IO_RANGE_TYPE_32        0x01
> -- 
> 1.6.0.2




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