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[Qemu-devel] [PATCH] target-mips: 4Kc, 4KEc cores do not support MIPS16
From: |
Stefan Weil |
Subject: |
[Qemu-devel] [PATCH] target-mips: 4Kc, 4KEc cores do not support MIPS16 |
Date: |
Tue, 15 Dec 2009 14:43:40 +0100 |
4Kc, 4KEc cores do not support MIPS16, so not only the
CP0_Config1 had to be fixed (see previous patch),
but also MIPS16 instructions must not be executed.
(Hint from Nathan Froyd, thanks).
Signed-off-by: Stefan Weil <address@hidden>
---
target-mips/translate_init.c | 6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index b710979..b79ed56 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -115,7 +115,7 @@ static const mips_def_t mips_defs[] =
.CP0_Status_rw_bitmask = 0x1278FF17,
.SEGBITS = 32,
.PABITS = 32,
- .insn_flags = CPU_MIPS32 | ASE_MIPS16,
+ .insn_flags = CPU_MIPS32,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -157,7 +157,7 @@ static const mips_def_t mips_defs[] =
.CP0_Status_rw_bitmask = 0x1278FF17,
.SEGBITS = 32,
.PABITS = 32,
- .insn_flags = CPU_MIPS32 | ASE_MIPS16,
+ .insn_flags = CPU_MIPS32,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -198,7 +198,7 @@ static const mips_def_t mips_defs[] =
.CP0_Status_rw_bitmask = 0x1278FF17,
.SEGBITS = 32,
.PABITS = 32,
- .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
+ .insn_flags = CPU_MIPS32R2,
.mmu_type = MMU_TYPE_R4000,
},
{
--
1.6.5
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