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[Qemu-devel] [PATCH 1/8] sh7750: handle MMUCR TI bit
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [PATCH 1/8] sh7750: handle MMUCR TI bit |
Date: |
Sat, 6 Feb 2010 17:43:36 +0100 |
When the MMUCR TI bit is set, all the UTLB and ITLB entries should be
flushed.
Signed-off-by: Aurelien Jarno <address@hidden>
---
hw/sh7750.c | 7 +++++--
target-sh4/cpu.h | 2 ++
target-sh4/helper.c | 18 ++++++++++++++++++
3 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/hw/sh7750.c b/hw/sh7750.c
index 933bbc0..9c39f4b 100644
--- a/hw/sh7750.c
+++ b/hw/sh7750.c
@@ -396,8 +396,11 @@ static void sh7750_mem_writel(void *opaque,
target_phys_addr_t addr,
portb_changed(s, temp);
return;
case SH7750_MMUCR_A7:
- s->cpu->mmucr = mem_value;
- return;
+ if (mem_value & MMUCR_TI) {
+ cpu_sh4_invalidate_tlb(s->cpu);
+ }
+ s->cpu->mmucr = mem_value & ~MMUCR_TI;
+ return;
case SH7750_PTEH_A7:
/* If asid changes, clear all registered tlb entries. */
if ((s->cpu->pteh & 0xff) != (mem_value & 0xff))
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index 366e798..015d598 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -167,6 +167,7 @@ int cpu_sh4_handle_mmu_fault(CPUSH4State * env,
target_ulong address, int rw,
void do_interrupt(CPUSH4State * env);
void sh4_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
+void cpu_sh4_invalidate_tlb(CPUSH4State *s);
void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
uint32_t mem_value);
@@ -222,6 +223,7 @@ enum {
/* MMU control register */
#define MMUCR 0x1F000010
#define MMUCR_AT (1<<0)
+#define MMUCR_TI (1<<2)
#define MMUCR_SV (1<<8)
#define MMUCR_URC_BITS (6)
#define MMUCR_URC_OFFSET (10)
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index 088d36a..e7c494f 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -574,6 +574,24 @@ void cpu_load_tlb(CPUSH4State * env)
entry->tc = (uint8_t)cpu_ptea_tc(env->ptea);
}
+ void cpu_sh4_invalidate_tlb(CPUSH4State *s)
+{
+ int i;
+
+ /* UTLB */
+ for (i = 0; i < UTLB_SIZE; i++) {
+ tlb_t * entry = &s->utlb[i];
+ entry->v = 0;
+ }
+ /* ITLB */
+ for (i = 0; i < UTLB_SIZE; i++) {
+ tlb_t * entry = &s->utlb[i];
+ entry->v = 0;
+ }
+
+ tlb_flush(s, 1);
+}
+
void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
uint32_t mem_value)
{
--
1.6.6.1
- [Qemu-devel] [PATCH 0/8] SH4 MMU fixes and optimisation, Aurelien Jarno, 2010/02/06
- [Qemu-devel] [PATCH 7/8] target-sh4: MMU: remove dead code, Aurelien Jarno, 2010/02/06
- [Qemu-devel] [PATCH 2/8] target-sh4: MMU: fix mem_idx computation, Aurelien Jarno, 2010/02/06
- [Qemu-devel] [PATCH 6/8] target-sh4: MMU: reduce the size of a TLB entry, Aurelien Jarno, 2010/02/06
- [Qemu-devel] [PATCH 8/8] target-sh4: MMU: fix store queue addresses, Aurelien Jarno, 2010/02/06
- [Qemu-devel] [PATCH 3/8] target-sh4: MMU: simplify call to tlb_set_page(), Aurelien Jarno, 2010/02/06
- [Qemu-devel] [PATCH 1/8] sh7750: handle MMUCR TI bit,
Aurelien Jarno <=
- [Qemu-devel] [PATCH 5/8] target-sh4: MMU: optimize UTLB accesses, Aurelien Jarno, 2010/02/06
- [Qemu-devel] [PATCH 4/8] target-sh4: MMU: fix ITLB priviledge check, Aurelien Jarno, 2010/02/06