[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-devel] Re: [PATCH 2/6] qemu-kvm: Modify and introduce wrapper

From: Avi Kivity
Subject: Re: [Qemu-devel] Re: [PATCH 2/6] qemu-kvm: Modify and introduce wrapper functions to access phys_ram_dirty.
Date: Wed, 17 Mar 2010 18:28:03 +0200
User-agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv: Gecko/20100301 Fedora/3.0.3-1.fc12 Thunderbird/3.0.3

On 03/17/2010 06:06 PM, Paul Brook wrote:
On 03/16/2010 10:10 PM, Blue Swirl wrote:
   Yes, and is what tlb_protect_code() does and it's called from
tb_alloc_page() which is what's code when a TB is created.
Just a tangential note: a long time ago, I tried to disable self
modifying code detection for Sparc. On most RISC architectures, SMC
needs explicit flushing so in theory we need not track code memory
writes. However, during exceptions the translator needs to access the
original unmodified code that was used to generate the TB. But maybe
there are other ways to avoid SMC tracking, on x86 it's still needed
On x86 you're supposed to execute a serializing instruction (one of
register, with the exception of MOV CR8), MOV (to debug register),
WBINVD, WRMSR, CPUID, IRET, and RSM) before running modified code.
Last time I checked, a jump instruction was sufficient to ensure coherency
withing a core.  Serializing instructions are only required for coherency
between cores on SMP systems.

Yeah, the docs say either a jump or a serializing instruction is needed.

QEMU effectively has a very large physically tagged icache[1] with very
expensive cache loads.  AFAIK The only practical way to maintain that cache on
x86 targets is to do write snooping via dirty bits. On targets that mandate
explicit icache invalidation we might be able to get away with this, however I
doubt it actually gains you anything - a correctly written guest is going to
invalidate at least as much as we get from dirty tracking, and we still need
to provide correct behaviour when executing with cache disabled.


but I suppose SMC is pretty rare.
Every time you demand load a code page from disk, you're running self
modifying code (though it usually doesn't exist in the tlb, so there's
no previous version that can cause trouble).
I think you're confusing TLB flushes with TB flushes.

No - my thinking was page fault, load page, invlpg, continue. But the invlpg is unneeded, and "continue" has to include a jump anyway.

error compiling committee.c: too many arguments to function

reply via email to

[Prev in Thread] Current Thread [Next in Thread]