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[Qemu-devel] [PATCH 6/6] tcg-hppa: Remove automatically implemented opco
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 6/6] tcg-hppa: Remove automatically implemented opcodes. |
Date: |
Sat, 10 Apr 2010 22:22:28 +0200 |
Remove neg, ext8u, ext16u, as requested.
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/hppa/tcg-target.c | 16 ----------------
tcg/hppa/tcg-target.h | 8 +++++---
2 files changed, 5 insertions(+), 19 deletions(-)
diff --git a/tcg/hppa/tcg-target.c b/tcg/hppa/tcg-target.c
index 6536a42..cb605f1 100644
--- a/tcg/hppa/tcg-target.c
+++ b/tcg/hppa/tcg-target.c
@@ -1431,19 +1431,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc, const TCGArg *args,
tcg_out_ext16s(s, args[0], args[1]);
break;
- /* These three correspond exactly to the fallback implementation.
- But by including them we reduce the number of TCG ops that
- need to be generated, and these opcodes are fairly common. */
- case INDEX_op_neg_i32:
- tcg_out_arith(s, args[0], TCG_REG_R0, args[1], INSN_SUB);
- break;
- case INDEX_op_ext8u_i32:
- tcg_out_andi(s, args[0], args[1], 0xff);
- break;
- case INDEX_op_ext16u_i32:
- tcg_out_andi(s, args[0], args[1], 0xffff);
- break;
-
case INDEX_op_brcond_i32:
tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], args[3]);
break;
@@ -1550,13 +1537,10 @@ static const TCGTargetOpDef hppa_op_defs[] = {
{ INDEX_op_bswap16_i32, { "r", "r" } },
{ INDEX_op_bswap32_i32, { "r", "r" } },
- { INDEX_op_neg_i32, { "r", "r" } },
{ INDEX_op_not_i32, { "r", "r" } },
{ INDEX_op_ext8s_i32, { "r", "r" } },
- { INDEX_op_ext8u_i32, { "r", "r" } },
{ INDEX_op_ext16s_i32, { "r", "r" } },
- { INDEX_op_ext16u_i32, { "r", "r" } },
{ INDEX_op_brcond_i32, { "rZ", "rJ" } },
{ INDEX_op_brcond2_i32, { "rZ", "rZ", "rJ", "rJ" } },
diff --git a/tcg/hppa/tcg-target.h b/tcg/hppa/tcg-target.h
index 7e21f1d..a5cc440 100644
--- a/tcg/hppa/tcg-target.h
+++ b/tcg/hppa/tcg-target.h
@@ -89,15 +89,17 @@ enum {
#define TCG_TARGET_HAS_rot_i32
#define TCG_TARGET_HAS_ext8s_i32
#define TCG_TARGET_HAS_ext16s_i32
-#define TCG_TARGET_HAS_ext8u_i32
-#define TCG_TARGET_HAS_ext16u_i32
#define TCG_TARGET_HAS_bswap16_i32
#define TCG_TARGET_HAS_bswap32_i32
#define TCG_TARGET_HAS_not_i32
-#define TCG_TARGET_HAS_neg_i32
#define TCG_TARGET_HAS_andc_i32
// #define TCG_TARGET_HAS_orc_i32
+/* optional instructions automatically implemented */
+#undef TCG_TARGET_HAS_neg_i32 /* sub rd, 0, rs */
+#undef TCG_TARGET_HAS_ext8u_i32 /* and rd, rs, 0xff */
+#undef TCG_TARGET_HAS_ext16u_i32 /* and rd, rs, 0xffff */
+
#define TCG_TARGET_HAS_GUEST_BASE
/* Note: must be synced with dyngen-exec.h */
--
1.6.2.5
- [Qemu-devel] [PATCH 0/6] tcg-hppa improvements, Richard Henderson, 2010/04/14
- [Qemu-devel] [PATCH 4/6] tcg-hppa: Schedule the address masking after the TLB load., Richard Henderson, 2010/04/14
- [Qemu-devel] [PATCH 2/6] tcg-hppa: Fix GUEST_BASE initialization in prologue., Richard Henderson, 2010/04/14
- [Qemu-devel] [PATCH 5/6] tcg-hppa: Fix branch offset during retranslation., Richard Henderson, 2010/04/14
- [Qemu-devel] [PATCH 6/6] tcg-hppa: Remove automatically implemented opcodes.,
Richard Henderson <=
- [Qemu-devel] [PATCH 3/6] tcg-hppa: Fix softmmu loads and stores., Richard Henderson, 2010/04/14
- [Qemu-devel] [PATCH 1/6] tcg-hppa: Constrain immediate inputs to and_i32, or_i32, andc_i32., Richard Henderson, 2010/04/14
- [Qemu-devel] Re: [PATCH 0/6] tcg-hppa improvements, Paolo Bonzini, 2010/04/14