Re: [Qemu-devel] [PATCH v2 4/5] target-ppc: fix RFI by clearing upper bytes of MSR

[Thomas Monjalon]

Alexander Graf wrote:
> Thomas Monjalon wrote:
> > I'm running Linux for SBC834x in Qemu. The interrupt controller and board
> > definition are not yet published.
>
> Wow, I didn't know there were still new products based on e300.

Sorry, I was not clear. By "not yet published", I mean that I've written Qemu 
code to emulate e300 but I haven't yet send it to the ML. I would prefer to 
fix this RFI issue first.
SBC834x is not a new product.


> > From the e300 reference manual (e300CORERM):
> > "The TGPR bit is cleared by an rfi instruction."
> >
> > My first try was to clear only TGPR. But it doesn't work properly if POW
> > and ILE are not cleared.
>
> According to the 2.06 ISA again, rfi does the following:
>
> The contents of SRR1 are placed into the MSR. If the new MSR value does
> not enable any pending exceptions, then the next instruction is fetched,
> under control of the new MSR value, from the address SRR0 0:64 || 0b00.
>
> If rfi would clear ILE, how would it be enabled then?

You should be right. I have to fix a bug elsewhere.

-- 
Thomas