[Qemu-devel] [PATCH 24/62] tcg-s390: Implement div2.

[Richard Henderson]

The s390 divide instructions always produce both remainder and quotient.
Since TCG has no mechanism for allocating even+odd register pairs, force
the use of the R2/R3 register pair.

Signed-off-by: Richard Henderson <address@hidden>
---
 tcg/s390/tcg-target.c |   44 ++++++++++++++++++++++++++++++--------------
 tcg/s390/tcg-target.h |    4 ++--
 2 files changed, 32 insertions(+), 16 deletions(-)

diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c
index 0bd4276..4c2acca 100644
--- a/tcg/s390/tcg-target.c
+++ b/tcg/s390/tcg-target.c
@@ -75,6 +75,7 @@ typedef enum S390Opcode {
     RR_BCR      = 0x07,
     RR_CLR      = 0x15,
     RR_CR       = 0x19,
+    RR_DR       = 0x1d,
     RR_LCR      = 0x13,
     RR_LR       = 0x18,
     RR_NR       = 0x14,
@@ -258,6 +259,14 @@ static int target_parse_constraint(TCGArgConstraint *ct, 
const char **pct_str)
     case 'R':                        /* not R0 */
         tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
         break;
+    case 'a':                  /* force R2 for division */
+        tcg_regset_clear(ct->u.regs);
+        tcg_regset_set_reg(ct->u.regs, TCG_REG_R2);
+        break;
+    case 'b':                  /* force R3 for division */
+        tcg_regset_clear(ct->u.regs);
+        tcg_regset_set_reg(ct->u.regs, TCG_REG_R3);
+        break;
     case 'I':
         ct->ct &= ~TCG_CT_REG;
         ct->ct |= TCG_CT_CONST_S16;
@@ -946,16 +955,22 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode 
opc,
         tcg_out_insn(s, RRE, MSGR, args[0], args[2]);
         break;
 
-    case INDEX_op_divu_i32:
-    case INDEX_op_remu_i32:
-        tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R12, 0);
-        tcg_out_insn(s, RR, LR, TCG_REG_R13, args[1]);
-        tcg_out_insn(s, RRE, DLR, TCG_REG_R12, args[2]);
-        if (opc == INDEX_op_divu_i32) {
-          tcg_out_insn(s, RR, LR, args[0], TCG_REG_R13);        /* quotient */
-        } else {
-          tcg_out_insn(s, RR, LR, args[0], TCG_REG_R12);        /* remainder */
-        }
+    case INDEX_op_div2_i32:
+        tcg_out_insn(s, RR, DR, TCG_REG_R2, args[4]);
+        break;
+    case INDEX_op_divu2_i32:
+        tcg_out_insn(s, RRE, DLR, TCG_REG_R2, args[4]);
+        break;
+
+    case INDEX_op_div2_i64:
+        /* ??? We get an unnecessary sign-extension of the dividend
+           into R3 with this definition, but as we do in fact always
+           produce both quotient and remainder using INDEX_op_div_i64
+           instead requires jumping through even more hoops.  */
+        tcg_out_insn(s, RRE, DSGR, TCG_REG_R2, args[4]);
+        break;
+    case INDEX_op_divu2_i64:
+        tcg_out_insn(s, RRE, DLGR, TCG_REG_R2, args[4]);
         break;
 
     case INDEX_op_shl_i32:
@@ -1085,10 +1100,8 @@ static const TCGTargetOpDef s390_op_defs[] = {
     { INDEX_op_sub_i32, { "r", "0", "r" } },
     { INDEX_op_mul_i32, { "r", "0", "r" } },
 
-    { INDEX_op_div_i32, { "r", "r", "r" } },
-    { INDEX_op_divu_i32, { "r", "r", "r" } },
-    { INDEX_op_rem_i32, { "r", "r", "r" } },
-    { INDEX_op_remu_i32, { "r", "r", "r" } },
+    { INDEX_op_div2_i32, { "b", "a", "0", "1", "r" } },
+    { INDEX_op_divu2_i32, { "b", "a", "0", "1", "r" } },
 
     { INDEX_op_and_i32, { "r", "0", "r" } },
     { INDEX_op_or_i32, { "r", "0", "r" } },
@@ -1137,6 +1150,9 @@ static const TCGTargetOpDef s390_op_defs[] = {
     { INDEX_op_sub_i64, { "r", "0", "r" } },
     { INDEX_op_mul_i64, { "r", "0", "r" } },
 
+    { INDEX_op_div2_i64, { "b", "a", "0", "1", "r" } },
+    { INDEX_op_divu2_i64, { "b", "a", "0", "1", "r" } },
+
     { INDEX_op_and_i64, { "r", "0", "r" } },
     { INDEX_op_or_i64, { "r", "0", "r" } },
     { INDEX_op_xor_i64, { "r", "0", "r" } },
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index c81f886..b987a7e 100644
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -48,7 +48,7 @@ typedef enum TCGReg {
 #define TCG_TARGET_NB_REGS 16
 
 /* optional instructions */
-#define TCG_TARGET_HAS_div_i32
+#define TCG_TARGET_HAS_div2_i32
 // #define TCG_TARGET_HAS_rot_i32
 // #define TCG_TARGET_HAS_ext8s_i32
 // #define TCG_TARGET_HAS_ext16s_i32
@@ -64,7 +64,7 @@ typedef enum TCGReg {
 // #define TCG_TARGET_HAS_nand_i32
 // #define TCG_TARGET_HAS_nor_i32
 
-// #define TCG_TARGET_HAS_div_i64
+#define TCG_TARGET_HAS_div2_i64
 // #define TCG_TARGET_HAS_rot_i64
 // #define TCG_TARGET_HAS_ext8s_i64
 // #define TCG_TARGET_HAS_ext16s_i64
-- 
1.7.0.1