Re: [Qemu-devel] [PATCH 08/12] ARM: Return correct result for single<->double conversion of NaN

[Nathan Froyd]

On Tue, Nov 23, 2010 at 06:53:47PM +0000, Peter Maydell wrote:
> The ARM ARM defines that if the input to a single<->double conversion
> is a NaN then the output is always forced to be a quiet NaN by setting
> the most significant bit of the fraction part.
> 
> Signed-off-by: Peter Maydell <address@hidden>
> 
> @@ -2529,12 +2529,26 @@ float32 VFP_HELPER(tosiz, d)(float64 x, CPUState *env)
>  /* floating point conversion */
>  float64 VFP_HELPER(fcvtd, s)(float32 x, CPUState *env)
>  {
> -    return float32_to_float64(x, &env->vfp.fp_status);
> +    float64 r = float32_to_float64(x, &env->vfp.fp_status);
> +    /* ARM requires that S<->D conversion of any kind of NaN generates
> +     * a quiet NaN by forcing the most significant frac bit to 1.
> +     */
> +    if (float64_is_signaling_nan(r)) {
> +        return make_float64(float64_val(r) | (1LL << 51));
> +    }
> +    return r;
>  }

As with other NaN-handling patches, I don't think the bit-twiddling here
is a good idea.  Having a float*_maybe_silence_nan function in softfloat
would be a better approach.

-Nathan