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Re: [Qemu-devel] [PATCH 0/6] [RFC] New SPARC machine: Leon3

From: Fabien Chouteau
Subject: Re: [Qemu-devel] [PATCH 0/6] [RFC] New SPARC machine: Leon3
Date: Tue, 07 Dec 2010 18:43:12 +0100
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On 12/06/2010 07:12 PM, Blue Swirl wrote:
On Mon, Dec 6, 2010 at 3:07 PM, Fabien Chouteau<address@hidden>  wrote:
On 12/06/2010 11:44 AM, Artyom Tarasenko wrote:

On Mon, Dec 6, 2010 at 10:26 AM, Fabien Chouteau<address@hidden>

Hi everyone,
I'm glad to submit my first patches to the Qemu-devel list.

This patch set introduces a new SPARC V8 machine: Leon3. It's an
VHDL System-On-Chip, well known in space industry (more information on

Nice! Haven't looked into the code yet, but it's great to have someone
who cares for V8.

And if this patch is accepted, we will try to submit more machines like
erc32 and leon2.

Do you also have a firmware which runs on these machines?

I can give you a binary running some basic tests.

Is the binary generally available?

No it's just a program that I use to test my work.

Otherwise it would be very hard to
test any changes and the code would bitrot. I'm not sure we even want
to support such machines.

I think we can find many people interested in Leon3, the processor is well
known in the space industry and used in many research projects. The only
emulator available is Tsim and it's not free nor open-source, so Qemu has a
real interest here.

Are the sources available? That would help debugging.

I can give you the sources but it will be difficult for you to compile them.
It's an Ada program compiled with Gnat Pro for Leon3, using the Ravenscar
run-time. If you are not familiar with the Ada language, you can see the
Ravenscar run-time as a very small kernel providing basic tasking support for
safety critical applications.

Leon3 is made of multiple components available in the GrLib VHDL library.
Three devices are implemented: uart, timers and IRQ manager.
You can find code for these peripherals in the grlib_* files.

Modifications have been done to the SPARC cpu emulation code to handle
Leon3's specific behavior:
  - IRQ management
  - Cache control
  - Asr17 (implementation-dependent Ancillary State Registers)

Is it the only implementation-dependent asr in Leon3? Thought there were

Yes, there's also asr19 for power-down, asr16 for FPU control and others for
hardware breakpoints.
These are not required for this first implementation, but If there's a need
for more ASRs, we may have to find a generic implementation to handle those

So far I'd handle these in target-sparc/op_helper.c. If the registers
are also available as MMIO like MXCC, then we should invent a way to
handle both.

I don't see what you mean by "also available as MMIO", it's just regular
registers in the CPU, except that they are available for
implementation-dependent uses.

Thank you for your review ;)

Fabien Chouteau

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