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Re: [Qemu-devel] [PATCH v2 2/6] Emulation of GRLIB IRQMP as defined in G
From: |
Blue Swirl |
Subject: |
Re: [Qemu-devel] [PATCH v2 2/6] Emulation of GRLIB IRQMP as defined in GRLIB IP Core User's Manual. |
Date: |
Tue, 4 Jan 2011 19:02:08 +0000 |
On Mon, Jan 3, 2011 at 2:07 PM, Fabien Chouteau <address@hidden> wrote:
>
> Signed-off-by: Fabien Chouteau <address@hidden>
> ---
> hw/grlib_irqmp.c | 402
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++
> 1 files changed, 402 insertions(+), 0 deletions(-)
>
> diff --git a/hw/grlib_irqmp.c b/hw/grlib_irqmp.c
> new file mode 100644
> index 0000000..9f947d1
> --- /dev/null
> +++ b/hw/grlib_irqmp.c
> @@ -0,0 +1,402 @@
> +/*
> + * QEMU GRLIB IRQMP Emulator
> + *
> + * (Multiprocessor and extended interrupt not supported)
> + *
> + * Copyright (c) 2010-2011 AdaCore
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> copy
> + * of this software and associated documentation files (the "Software"), to
> deal
> + * in the Software without restriction, including without limitation the
> rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "sysbus.h"
> +#include "cpu.h"
> +
> +#include "grlib.h"
> +
> +//#define DEBUG_IRQ
> +
> +#ifdef DEBUG_IRQ
> +#define DPRINTF(fmt, ...) \
> + do { printf("IRQMP: " fmt , ## __VA_ARGS__); } while (0)
> +#else
> +#define DPRINTF(fmt, ...)
> +#endif
> +
> +#define IRQMP_MAX_CPU 16
> +#define IRQMP_REG_SIZE 256 /* Size of memory mapped registers */
> +
> +/* Memory mapped register offsets */
> +#define LEVEL_OFFSET 0x00
> +#define PENDING_OFFSET 0x04
> +#define FORCE0_OFFSET 0x08
> +#define CLEAR_OFFSET 0x0C
> +#define MP_STATUS_OFFSET 0x10
> +#define BROADCAST_OFFSET 0x14
> +#define MASK_OFFSET 0x40
> +#define FORCE_OFFSET 0x80
> +#define EXTENDED_OFFSET 0xC0
> +
> +typedef struct IRQMPState IRQMPState;
> +
> +typedef struct IRQMP
> +{
> + SysBusDevice busdev;
> +
> + CPUSPARCState *env;
No.
> +
> + IRQMPState *state;
> +} IRQMP;
> +
> +struct IRQMPState
> +{
> + uint32_t level;
> + uint32_t pending;
> + uint32_t clear;
> + uint32_t broadcast;
> +
> + uint32_t mask[IRQMP_MAX_CPU];
> + uint32_t force[IRQMP_MAX_CPU];
> + uint32_t extended[IRQMP_MAX_CPU];
> +
> + IRQMP *parent;
> +};
> +
> +static void grlib_irqmp_check_irqs(IRQMPState *state)
> +{
> + assert(state != NULL);
> + CPUState *env = state->parent->env;
> + assert(env != NULL);
> +
> + uint32_t pend = 0;
> + uint32_t level0 = 0;
> + uint32_t level1 = 0;
> +
> +
> + /* IRQ for CPU 0 (no SMP support) */
> + pend = (state->pending | state->force[0])
> + & state->mask[0];
> +
> +
> + level0 = pend & ~state->level;
> + level1 = pend & state->level;
> +
> + DPRINTF("pend:0x%04x force:0x%04x mask:0x%04x lvl1:0x%04x lvl0:0x%04x\n",
> + state->pending, state->force[0],
> + state->mask[0], level1, level0);
> +
> + /* Trigger level1 interrupt first and level0 if there is no level1 */
> + if (level1 != 0) {
> + env->pil_in = level1;
> + } else {
> + env->pil_in = level0;
> + }
> +
> + if (env->pil_in && (env->interrupt_index == 0 ||
> + (env->interrupt_index & ~15) == TT_EXTINT)) {
> + unsigned int i;
> +
> + for (i = 15; i > 0; i--) {
> + if (env->pil_in & (1 << i)) {
> + int old_interrupt = env->interrupt_index;
> +
> + env->interrupt_index = TT_EXTINT | i;
> + if (old_interrupt != env->interrupt_index) {
> + DPRINTF("Set CPU IRQ %d\n", i);
> + cpu_interrupt(env, CPU_INTERRUPT_HARD);
> + }
> + break;
> + }
> + }
> + } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
> + DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
> + env->interrupt_index = 0;
> + cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
> + }
> +}
> +
> +void grlib_irqmp_ack(DeviceState *dev, int intno)
> +{
> + assert(dev != NULL);
> +
> + SysBusDevice *sdev = sysbus_from_qdev(dev);
> + assert(sdev != NULL);
> +
> + IRQMP *irqmp = FROM_SYSBUS(typeof (*irqmp), sdev);
> + assert(irqmp != NULL);
> +
> + IRQMPState *state = irqmp->state;
> + assert(state != NULL);
> +
> + uint32_t mask;
> +
> + intno &= 15;
> + mask = 1 << intno;
> +
> + DPRINTF("grlib_irqmp_ack %d\n", intno);
> +
> + /* Clear registers */
> + state->pending &= ~mask;
> + state->force[0] &= ~mask; /* Only CPU 0 (No SMP support) */
> +
> + grlib_irqmp_check_irqs(state);
> +}
> +
> +void grlib_irqmp_set_irq(void *opaque, int irq, int level)
> +{
> + assert(opaque != NULL);
> +
> + IRQMP *irqmp = FROM_SYSBUS(typeof (*irqmp), sysbus_from_qdev(opaque));
> + assert(irqmp != NULL);
> +
> + IRQMPState *s = irqmp->state;
> + assert(s != NULL);
> + assert(s->parent != NULL);
> +
> + int i = 0;
Don't mix variable declarations with code (asserts).
> +
> +
> + if (level) {
> + DPRINTF("Raise CPU IRQ %d\n", irq);
> +
> + if (s->broadcast & 1 << irq) {
> + /* Broadcasted IRQ */
> + for (i = 0; i < IRQMP_MAX_CPU; i++) {
> + s->force[i] |= 1 << irq;
> + }
> + } else {
> + s->pending |= 1 << irq;
> + }
> + grlib_irqmp_check_irqs(s);
> +
> + }
> +}
> +
> +static uint32_t grlib_irqmp_readl(void *opaque, target_phys_addr_t addr)
> +{
> + IRQMP *irqmp = opaque;
> + assert(irqmp != NULL);
> +
> + IRQMPState *state = irqmp->state;
> + assert(state != NULL);
> +
> + addr &= 0xff;
Useless.
- [Qemu-devel] [PATCH v2 3/6] Emulation of GRLIB APB UART as defined in GRLIB IP Core User's Manual., (continued)
- [Qemu-devel] [PATCH v2 3/6] Emulation of GRLIB APB UART as defined in GRLIB IP Core User's Manual., Fabien Chouteau, 2011/01/03
- [Qemu-devel] [PATCH v2 4/6] Header file for the GRLIB components., Fabien Chouteau, 2011/01/03
- [Qemu-devel] [PATCH v2 5/6] Emulation of Leon3., Fabien Chouteau, 2011/01/03
- [Qemu-devel] [PATCH v2 6/6] SPARCV8 asr17 register support., Fabien Chouteau, 2011/01/03
- Re: [Qemu-devel] [PATCH v2 6/6] SPARCV8 asr17 register support., Blue Swirl, 2011/01/04
- Re: [Qemu-devel] [PATCH v2 5/6] Emulation of Leon3., Blue Swirl, 2011/01/04
- Re: [Qemu-devel] [PATCH v2 5/6] Emulation of Leon3., Fabien Chouteau, 2011/01/17
- Re: [Qemu-devel] [PATCH v2 5/6] Emulation of Leon3., Blue Swirl, 2011/01/17
- Re: [Qemu-devel] [PATCH v2 4/6] Header file for the GRLIB components., Blue Swirl, 2011/01/04
- Re: [Qemu-devel] [PATCH v2 3/6] Emulation of GRLIB APB UART as defined in GRLIB IP Core User's Manual., Blue Swirl, 2011/01/04
- Re: [Qemu-devel] [PATCH v2 2/6] Emulation of GRLIB IRQMP as defined in GRLIB IP Core User's Manual.,
Blue Swirl <=
Re: [Qemu-devel] [PATCH v2 1/6] Emulation of GRLIB GPTimer as defined in GRLIB IP Core User's Manual., Blue Swirl, 2011/01/04
Re: [Qemu-devel] [PATCH v2 0/6] [RFC] New SPARC machine: Leon3, Andreas Färber, 2011/01/04