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Re: [Qemu-devel] [PATCH 0/7] target-arm: Translate based on TB flags, no
From: |
Aurelien Jarno |
Subject: |
Re: [Qemu-devel] [PATCH 0/7] target-arm: Translate based on TB flags, not CPUState |
Date: |
Sat, 8 Jan 2011 16:00:24 +0100 |
User-agent: |
Mutt/1.5.18 (2008-05-17) |
On Fri, Jan 07, 2011 at 05:50:51PM +0000, Peter Maydell wrote:
> On 7 January 2011 16:01, Aurelien Jarno <address@hidden> wrote:
> > My other concern is about the definition of the individual bits in the
> > flags. I have seen that you have tried to summarize the usage in the
> > patch 6, but the masks and shifts are still duplicated in different
> > files, which may leads to mistakes if the flags definition are changed.
> >
> > Have you considered using #define as for example in the MIPS target?
>
> I'll put out a proper v2 patchset in a bit but to save a round,
> are you happy with the following set of #defines?
> (I'm going to drop the comment since the #defines give the
> same info.)
>
> /* Bit usage in the TB flags field: */
> #define ARM_TBFLAG_THUMB_SHIFT 0
> #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT)
> #define ARM_TBFLAG_VECLEN_SHIFT 1
> #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
> #define ARM_TBFLAG_VECSTRIDE_SHIFT 4
> #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
> #define ARM_TBFLAG_PRIV_SHIFT 6
> #define ARM_TBFLAG_PRIV_MASK (1 << ARM_TBFLAG_PRIV_SHIFT)
> #define ARM_TBFLAG_VFPEN_SHIFT 7
> #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT)
> #define ARM_TBFLAG_CONDEXEC_SHIFT 8
> #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
I am find with the names, maybe you can align the values for easier
readability, but that's details.
> /* some convenience accessor macros */
> #define ARM_TBFLAG_THUMB(F) \
> (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
> #define ARM_TBFLAG_VECLEN(F) \
> (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
> #define ARM_TBFLAG_VECSTRIDE(F) \
> (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
> #define ARM_TBFLAG_PRIV(F) \
> (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT)
> #define ARM_TBFLAG_VFPEN(F) \
> (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
> #define ARM_TBFLAG_CONDEXEC(F) \
> (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
>
Looks fine.
--
Aurelien Jarno GPG: 1024D/F1BCDB73
address@hidden http://www.aurel32.net
- [Qemu-devel] [PATCH 1/7] target-arm: Don't generate code specific to current CPU mode for SRS, (continued)
- [Qemu-devel] [PATCH 1/7] target-arm: Don't generate code specific to current CPU mode for SRS, Peter Maydell, 2011/01/07
- [Qemu-devel] [PATCH 5/7] target-arm: Translate with condexec bits from TB flags, not CPUState, Peter Maydell, 2011/01/07
- [Qemu-devel] [PATCH 7/7] target-arm: Translate with user-state from TB flags, not CPUState, Peter Maydell, 2011/01/07
- Re: [Qemu-devel] [PATCH 0/7] target-arm: Translate based on TB flags, not CPUState, Aurelien Jarno, 2011/01/07
- Re: [Qemu-devel] [PATCH 0/7] target-arm: Translate based on TB flags, not CPUState, Peter Maydell, 2011/01/07
- Re: [Qemu-devel] [PATCH 0/7] target-arm: Translate based on TB flags, not CPUState, Peter Maydell, 2011/01/07
- Re: [Qemu-devel] [PATCH 0/7] target-arm: Translate based on TB flags, not CPUState, Peter Maydell, 2011/01/07
- Re: [Qemu-devel] [PATCH 0/7] target-arm: Translate based on TB flags, not CPUState,
Aurelien Jarno <=