[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH 1/3] mips: Break TBs after mfc0_count
From: |
Edgar E. Iglesias |
Subject: |
Re: [Qemu-devel] [PATCH 1/3] mips: Break TBs after mfc0_count |
Date: |
Tue, 18 Jan 2011 11:43:17 +0100 |
User-agent: |
Mutt/1.5.20 (2009-06-14) |
On Tue, Jan 18, 2011 at 11:34:28AM +0100, Aurelien Jarno wrote:
> On Tue, Jan 18, 2011 at 12:29:40AM +0100, address@hidden wrote:
> > From: Edgar E. Iglesias <address@hidden>
> >
> > Break the TB after reading the count register. This makes it
> > possible to take timer interrupts immediately after a read of
> > a possibly expired timer.
> >
> > Signed-off-by: Edgar E. Iglesias <address@hidden>
> > ---
> > target-mips/translate.c | 4 +++-
> > 1 files changed, 3 insertions(+), 1 deletions(-)
> >
> > diff --git a/target-mips/translate.c b/target-mips/translate.c
> > index cce77be..313cc29 100644
> > --- a/target-mips/translate.c
> > +++ b/target-mips/translate.c
> > @@ -3410,8 +3410,10 @@ static void gen_mfc0 (CPUState *env, DisasContext
> > *ctx, TCGv arg, int reg, int s
> > gen_helper_mfc0_count(arg);
> > if (use_icount) {
> > gen_io_end();
> > - ctx->bstate = BS_STOP;
> > }
> > + /* Break the TB to be able to take timer interrupts immediately
> > + after reading count. */
> > + ctx->bstate = BS_STOP;
> > rn = "Count";
> > break;
> > /* 6,7 are implementation dependent */
>
> This looks fine, however it should probably be done the same way for
> dmfc0 on 64-bit MIPS.
You're right, I'll fix that. Thanks.