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Re: [Qemu-devel] [PATCH 28/35] kvm: x86: Introduce kvmclock device to sa


From: Anthony Liguori
Subject: Re: [Qemu-devel] [PATCH 28/35] kvm: x86: Introduce kvmclock device to save/restore its state
Date: Tue, 18 Jan 2011 10:37:34 -0600
User-agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Lightning/1.0b1 Thunderbird/3.0.10

On 01/18/2011 10:17 AM, Jan Kiszka wrote:
On 2011-01-18 17:04, Anthony Liguori wrote:
A KVM device should sit on a KVM specific bus that hangs off of
sysbus.
It can get to kvm_state through that bus.

That bus doesn't get instantiated through qdev so requiring a pointer
argument should not be an issue.



This design is in conflict with the requirement to attach KVM-assisted
devices also to their home bus, e.g. an assigned PCI device to the PCI
bus. We don't support multi-homed qdev devices.


The bus topology reflects how I/O flows in and out of a device.  We do
not model a perfect PC bus architecture and I don't think we ever intend
to.  Instead, we model a functional architecture.

I/O from an assigned device does not flow through the emulated PCI bus.
Therefore, it does not belong on the emulated PCI bus.

Assigned devices need to interact with the emulated PCI bus, but they
shouldn't be children of it.

You should be able to find assigned devices on some PCI bus, so you
either have to hack up the existing bus to host devices that are, on the
other side, not part of it or branch off a pci-kvm sub-bus, just like
you would have to create a sysbus-kvm.
Management tools should never transverse the device tree to find
devices.  This is a recipe for disaster in the long term because the
device tree will not remain stable.

So yes, a management tool should be able to enumerate assigned devices
as they would enumerate any other PCI device but that has almost nothing
to do with what the tree layout is.
I'm probably misunderstanding you, but if the bus topology as the guest
sees it is not properly reflected in an object tree on the qemu side, we
are creating hacks again.

There is no such thing as the "bus topology as the guest sees it".

The guest just sees a bunch of devices. The guest can only infer things like ISA busses. The guest sees a bunch of devices: an i8254, i8259, RTC, etc. Whether those devices are on an ISA bus, and LPC bus, or all in a SuperI/O chip that's part of the southbridge is all invisible to the guest.

The device model topology is 100% a hidden architectural detail.

Management and analysis tools must be able to traverse the system buses
and find guest devices this way.

We need to provide a compatible interface to the guest. If you agree with my above statements, then you'll also agree that we can do this without keeping the device model topology stable.

But we also need to provide a compatible interface to management tools. Exposing the device model topology as a compatible interface artificially limits us. It's far better to provide higher level supported interfaces to give us the flexibility to change the device model as we need to.

  If they create a device on bus X, it
must never end up on bus Y just because it happens to be KVM-assisted or
has some other property.

Nope.  This is exactly what should happen.

90% of the devices in the device model are not created by management tools. They're part of a chipset. The chipset has well defined extension points and we provide management interfaces to create devices on those extension points. That is, interfaces to create PCI devices.

Regards,

Anthony Liguori

  On the other hand, trying to hide this
dependency will likely cause severe damage to the qdev design.

Jan





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