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[Qemu-devel] [PATCH 03/13] target-arm: Simplify three-register pairwise
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 03/13] target-arm: Simplify three-register pairwise code |
Date: |
Mon, 11 Apr 2011 16:26:13 +0100 |
From: Juha Riihimäki <address@hidden>
Since we know that the case of (pairwise && q) has been caught
earlier, we can simplify the register setup code for each pass
in the three-register-same-size Neon loop.
Signed-off-by: Juha Riihimäki <address@hidden>
---
target-arm/translate.c | 19 ++++++++-----------
1 files changed, 8 insertions(+), 11 deletions(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 5ffbace..0cf933d 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -4328,7 +4328,6 @@ static int disas_neon_data_insn(CPUState * env,
DisasContext *s, uint32_t insn)
int count;
int pairwise;
int u;
- int n;
uint32_t imm, mask;
TCGv tmp, tmp2, tmp3, tmp4, tmp5;
TCGv_i64 tmp64;
@@ -4480,16 +4479,12 @@ static int disas_neon_data_insn(CPUState * env,
DisasContext *s, uint32_t insn)
if (pairwise) {
/* Pairwise. */
- if (q)
- n = (pass & 1) * 2;
- else
- n = 0;
- if (pass < q + 1) {
- tmp = neon_load_reg(rn, n);
- tmp2 = neon_load_reg(rn, n + 1);
+ if (pass < 1) {
+ tmp = neon_load_reg(rn, 0);
+ tmp2 = neon_load_reg(rn, 1);
} else {
- tmp = neon_load_reg(rm, n);
- tmp2 = neon_load_reg(rm, n + 1);
+ tmp = neon_load_reg(rm, 0);
+ tmp2 = neon_load_reg(rm, 1);
}
} else {
/* Elementwise. */
@@ -5147,6 +5142,7 @@ static int disas_neon_data_insn(CPUState * env,
DisasContext *s, uint32_t insn)
/* VMOV, VMVN. */
tmp = tcg_temp_new_i32();
if (op == 14 && invert) {
+ int n;
uint32_t val;
val = 0;
for (n = 0; n < 4; n++) {
@@ -5575,6 +5571,7 @@ static int disas_neon_data_insn(CPUState * env,
DisasContext *s, uint32_t insn)
break;
case 33: /* VTRN */
if (size == 2) {
+ int n;
for (n = 0; n < (q ? 4 : 2); n += 2) {
tmp = neon_load_reg(rm, n);
tmp2 = neon_load_reg(rd, n + 1);
@@ -5866,7 +5863,7 @@ static int disas_neon_data_insn(CPUState * env,
DisasContext *s, uint32_t insn)
}
} else if ((insn & (1 << 10)) == 0) {
/* VTBL, VTBX. */
- n = ((insn >> 5) & 0x18) + 8;
+ int n = ((insn >> 5) & 0x18) + 8;
if (insn & (1 << 6)) {
tmp = neon_load_reg(rd, 0);
} else {
--
1.7.1
- [Qemu-devel] [PATCH 00/13] ARM: Handle UNDEF cases in Neon data processing insns, Peter Maydell, 2011/04/11
- [Qemu-devel] [PATCH 03/13] target-arm: Simplify three-register pairwise code,
Peter Maydell <=
- [Qemu-devel] [PATCH 08/13] target-arm: Handle UNDEF cases for Neon 2 regs + scalar forms, Peter Maydell, 2011/04/11
- [Qemu-devel] [PATCH 11/13] target-arm: Handle UNDEF cases for Neon 2 register misc forms, Peter Maydell, 2011/04/11
- [Qemu-devel] [PATCH 09/13] target-arm: Handle UNDEF cases for VEXT, Peter Maydell, 2011/04/11
- [Qemu-devel] [PATCH 12/13] target-arm: Treat UNPREDICTABLE VTBL, VTBX case as UNDEF, Peter Maydell, 2011/04/11
- [Qemu-devel] [PATCH 05/13] target-arm: Collapse VSRI case into VSHL, VSLI, Peter Maydell, 2011/04/11
- [Qemu-devel] [PATCH 13/13] target-arm: Handle UNDEF cases for VDUP (scalar), Peter Maydell, 2011/04/11
- [Qemu-devel] [PATCH 06/13] target-arm: Handle UNDEF cases for Neon invalid modified-immediates, Peter Maydell, 2011/04/11
- [Qemu-devel] [PATCH 01/13] target-arm: Use lookup table for size check on Neon 3-reg-same insns, Peter Maydell, 2011/04/11