Re: [Qemu-devel] [PATCH] Add e500 instructions dcblc, dcbtls and dcbtstl as no-op

[Scott Wood]

On Thu, 30 Jun 2011 10:25:31 +0200
Fabien Chouteau <address@hidden> wrote:

> On 28/06/2011 18:20, Scott Wood wrote:
> > On Tue, 28 Jun 2011 10:17:39 +0200
> > Fabien Chouteau <address@hidden> wrote:
> > 
> >> Why do you want to set this bit? Can't we consider that the instruction is
> >> always effective?
> > 
> > But it's not.  Why claim it is, in the absence of some specific workload
> > that needs to be fooled (which could take many different forms, not all of
> > which are appropriate defaults)?
> 
> Reading the e500 manual again, it's not clear to me what can make the
> L1CSR0[CUL] to be set. If you have a better understanding, can you please
> explain?
> 

L1CSR0[CUL] is set whenever a lock set instruction fails to lock
(typically because all ways of the set are already locked).  Since we don't
support cache locking in qemu, these instructions always fail, and thus CUL
should always be set.

Regarding what behavior would maximize compatibility, while it's
conceivable that some program could break if it sees the bit set when it
was expecting to be able to succeed, also consider a program that might
keep locking until it sees the bit set to determine how much cache it can
lock.

-Scott