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[Qemu-devel] [PATCH 018/111] m68k: add word data size for suba/adda
From: |
Bryce Lanham |
Subject: |
[Qemu-devel] [PATCH 018/111] m68k: add word data size for suba/adda |
Date: |
Wed, 17 Aug 2011 15:46:23 -0500 |
From: Laurent Vivier <address@hidden>
Allows suba and adda to manage word sized effective address, and attach
them to M68000 feature.
Signed-off-by: Andreas Schwab <address@hidden>
Signed-off-by: Laurent Vivier <address@hidden>
---
target-m68k/translate.c | 6 ++++--
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 74faabf..0321349 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -1881,7 +1881,7 @@ DISAS_INSN(suba)
TCGv src;
TCGv reg;
- SRC_EA(src, OS_LONG, 0, NULL);
+ SRC_EA(src, (insn & 0x100) ? OS_LONG : OS_WORD, -1, NULL);
reg = AREG(insn, 9);
tcg_gen_sub_i32(reg, reg, src);
}
@@ -1991,7 +1991,7 @@ DISAS_INSN(adda)
TCGv src;
TCGv reg;
- SRC_EA(src, OS_LONG, 0, NULL);
+ SRC_EA(src, (insn & 0x100) ? OS_LONG : OS_WORD, -1, NULL);
reg = AREG(insn, 9);
tcg_gen_add_i32(reg, reg, src);
}
@@ -3109,6 +3109,7 @@ void register_m68k_insns (CPUM68KState *env)
INSN(subx, 9180, f1f8, CF_ISA_A);
INSN(subx, 9100, f138, M68000);
INSN(suba, 91c0, f1c0, CF_ISA_A);
+ INSN(suba, 90c0, f0c0, M68000);
INSN(undef_mac, a000, f000, CF_ISA_A);
INSN(undef_mac, a000, f000, M68000);
@@ -3144,6 +3145,7 @@ void register_m68k_insns (CPUM68KState *env)
INSN(addx, d180, f1f8, CF_ISA_A);
INSN(addx, d100, f138, M68000);
INSN(adda, d1c0, f1c0, CF_ISA_A);
+ INSN(adda, d0c0, f0c0, M68000);
INSN(shift_im, e080, f0f0, CF_ISA_A);
INSN(shift_reg, e0a0, f0f0, CF_ISA_A);
INSN(shift_im, e080, f0f0, M68000);
--
1.7.2.3
- [Qemu-devel] [PATCH 008/111] linux-user: define default cpu model in configure instead of linux-user/main.c, (continued)
- [Qemu-devel] [PATCH 008/111] linux-user: define default cpu model in configure instead of linux-user/main.c, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 009/111] m68k: add tcg_gen_debug_insn_start(), Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 005/111] linux-user,m68k: display default cpu, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 010/111] m68k: define m680x0 CPUs and features, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 011/111] m68k: add missing accessing modes for some instructions., Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 013/111] m68k: add Scc instruction with memory operand., Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 012/111] m68k: add Motorola 680x0 family common instructions., Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 015/111] m68k: modify movem instruction to manage word, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 016/111] m68k: add 64bit divide., Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 014/111] m68k: add DBcc instruction., Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 018/111] m68k: add word data size for suba/adda,
Bryce Lanham <=
- [Qemu-devel] [PATCH 017/111] m68k: add 32bit and 64bit multiply, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 019/111] m68k: add fpu, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 020/111] m68k: add "byte", "word" and memory shift, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 022/111] m68k: add bitfield_mem, bitfield_reg, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 029/111] m68k: allow fpu to manage double data type with fmove to <ea>, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 030/111] m68k: add FScc instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 031/111] m68k: add single data type to gen_ea, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 039/111] m68k: add abcd instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 035/111] m68k: improve CC_OP_LOGIC, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 037/111] Correct invalid use of "const void *" with "const uint8_t *", Bryce Lanham, 2011/08/17