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[Qemu-devel] [PATCH 086/111] m68k: correct bfins instruction
From: |
Bryce Lanham |
Subject: |
[Qemu-devel] [PATCH 086/111] m68k: correct bfins instruction |
Date: |
Wed, 17 Aug 2011 15:47:31 -0500 |
From: Laurent Vivier <address@hidden>
correctly update generated condition code.
seen with gcc testsuite,
gcc-4.1.2/gcc/testsuite/gcc.c-torture/execute/960301-1.c
Signed-off-by: Laurent Vivier <address@hidden>
---
target-m68k/translate.c | 34 +++++++++++++++++++++++++++++-----
tests/m68k/Makefile | 3 ++-
tests/m68k/bfins.S | 23 +++++++++++++++++++++++
3 files changed, 54 insertions(+), 6 deletions(-)
create mode 100644 tests/m68k/bfins.S
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index d4445fe..96ea93f 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -3091,9 +3091,22 @@ DISAS_INSN(bitfield_reg)
tmp1 = tcg_temp_new_i32();
gen_helper_rol32(tmp1, tmp, offset);
- gen_logic_cc(s, tmp1, OS_LONG);
reg2 = DREG(ext, 12);
+ if (op == 7) {
+ TCGv tmp2;
+
+ tmp2 = tcg_temp_new_i32();
+ tcg_gen_sub_i32(tmp2, tcg_const_i32(32), width);
+ tcg_gen_shl_i32(tmp2, reg2, tmp2);
+ tcg_gen_and_i32(tmp2, tmp2, mask);
+ gen_logic_cc(s, tmp2, OS_LONG);
+
+ tcg_temp_free_i32(tmp1);
+ } else {
+ gen_logic_cc(s, tmp1, OS_LONG);
+ }
+
switch (op) {
case 0: /* bftst */
break;
@@ -3157,11 +3170,7 @@ static TCGv gen_bitfield_cc(DisasContext *s,
tcg_gen_shri_i64(tmp64, tmp64, 32ULL);
dest = tcg_temp_new_i32();
tcg_gen_trunc_i64_i32(dest, tmp64);
-
- /* compute cc */
-
tcg_gen_and_i32(dest, dest, mask_cc);
- gen_logic_cc(s, dest, OS_LONG);
return dest;
}
@@ -3283,6 +3292,21 @@ DISAS_INSN(bitfield_mem)
/* execute operation */
reg = DREG(ext, 12);
+
+ if (op == 7) {
+ TCGv tmp1;
+
+ tmp1 = tcg_temp_new_i32();
+ tcg_gen_sub_i32(tmp1, tcg_const_i32(32), width);
+ tcg_gen_shl_i32(tmp1, reg, tmp1);
+ tcg_gen_and_i32(tmp1, tmp1, mask_cc);
+ gen_logic_cc(s, tmp1, OS_LONG);
+
+ tcg_temp_free_i32(tmp1);
+ } else {
+ gen_logic_cc(s, val, OS_LONG);
+ }
+
switch (op) {
case 0: /* bftst */
break;
diff --git a/tests/m68k/Makefile b/tests/m68k/Makefile
index 8e90986..d043aeb 100644
--- a/tests/m68k/Makefile
+++ b/tests/m68k/Makefile
@@ -1,4 +1,5 @@
-TESTS=fmovecr fmove fmovem fsub fdiv fmul fabs fgetexp fscale flogn fetox
+TESTS=fmovecr fmove fmovem fsub fdiv fmul fabs fgetexp fscale flogn fetox \
+ bfins
all: $(TESTS)
diff --git a/tests/m68k/bfins.S b/tests/m68k/bfins.S
new file mode 100644
index 0000000..a0b27f9
--- /dev/null
+++ b/tests/m68k/bfins.S
@@ -0,0 +1,23 @@
+ .include "trap.i"
+
+ .data
+.A: .long 0
+ .text
+ .globl _start
+_start:
+ move.l #0,%d1
+ move.l #1,%d0
+ bfins %d0,%d1,4,4
+ move.l #3,%d0
+ bfins %d0,%d1,8,2
+ move.l #0,%d0
+ bfins %d0,%d1,8,16
+
+ move.l #1,%d0
+ lea .A,%a0
+ bfins %d0,(%a0),4,4
+ move.l #3,%d0
+ bfins %d0,(%a0),8,2
+ move.l #0,%d0
+ bfins %d0,(%a0),8,16
+ exit 0
--
1.7.2.3
- Re: [Qemu-devel] [RFC][PATCH 000/111] QEMU m68k core additions, (continued)
- Re: [Qemu-devel] [RFC][PATCH 000/111] QEMU m68k core additions, Rob Landley, 2011/08/20
- Re: [Qemu-devel] [RFC][PATCH 000/111] QEMU m68k core additions, Rob Landley, 2011/08/20
- Re: [Qemu-devel] [RFC][PATCH 000/111] QEMU m68k core additions, Rob Landley, 2011/08/20
- Re: [Qemu-devel] [RFC][PATCH 000/111] QEMU m68k core additions, Rob Landley, 2011/08/20
- Re: [Qemu-devel] [RFC][PATCH 000/111] QEMU m68k core additions, Laurent Vivier, 2011/08/20
- Re: [Qemu-devel] [RFC][PATCH 000/111] QEMU m68k core additions, Rob Landley, 2011/08/20
- Re: [Qemu-devel] [RFC][PATCH 000/111] QEMU m68k core additions, Rob Landley, 2011/08/20
- Re: [Qemu-devel] [RFC][PATCH 000/111] QEMU m68k core additions, Rob Landley, 2011/08/20
[Qemu-devel] [PATCH 086/111] m68k: correct bfins instruction,
Bryce Lanham <=
[Qemu-devel] [PATCH 025/111] m68k: add cas, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 067/111] m68k: add fscale, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 033/111] m68k: Add fmovecr, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 058/111] m68k: correctly compute divul, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 069/111] m68k: add fetox and flogn, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 048/111] m68k: correct shift side effect for roxrl and roxll, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 065/111] m68k: correct compute gen_bitfield_cc(), Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 049/111] m68k: asl/asr, clear C flag if shift count is 0, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 044/111] m68k: improve addx instructions Add (byte, word) opsize Add memory access, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 046/111] m68k: improve asl/asr evaluate correclty the missing V flag, Bryce Lanham, 2011/08/17