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[Qemu-devel] [PATCH 1/3] PPC: E500: Add ESR bit definitions
From: |
Alexander Graf |
Subject: |
[Qemu-devel] [PATCH 1/3] PPC: E500: Add ESR bit definitions |
Date: |
Tue, 23 Aug 2011 06:55:42 +0200 |
The BookE spec specifies a number of ESR bits. Add defines for them
so we can use them later on.
Reported-by: Jason Wessel <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
target-ppc/cpu.h | 17 ++++++++++++++++-
target-ppc/helper.c | 4 ++--
2 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 024eb6f..b8d42e0 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -516,7 +516,22 @@ struct ppc_slb_t {
#endif
/* Exception state register bits definition */
-#define ESR_ST 23 /* Exception was caused by a store type access. */
+#define ESR_PIL (1 << (63 - 36)) /* Illegal Instruction */
+#define ESR_PPR (1 << (63 - 37)) /* Privileged Instruction */
+#define ESR_PTR (1 << (63 - 38)) /* Trap */
+#define ESR_FP (1 << (63 - 39)) /* Floating-Point Operation */
+#define ESR_ST (1 << (63 - 40)) /* Store Operation */
+#define ESR_AP (1 << (63 - 44)) /* Auxiliary Processor Operation */
+#define ESR_PUO (1 << (63 - 45)) /* Unimplemented Operation */
+#define ESR_BO (1 << (63 - 46)) /* Byte Ordering */
+#define ESR_PIE (1 << (63 - 47)) /* Imprecise exception */
+#define ESR_DATA (1 << (63 - 53)) /* Data Access (Embedded page table) */
+#define ESR_TLBI (1 << (63 - 54)) /* TLB Ineligible (Embedded page table) */
+#define ESR_PT (1 << (63 - 55)) /* Page Table (Embedded page table) */
+#define ESR_SPV (1 << (63 - 56)) /* SPE/VMX operation */
+#define ESR_EPID (1 << (63 - 57)) /* External Process ID operation */
+#define ESR_VLEMI (1 << (63 - 58)) /* VLE operation */
+#define ESR_MIF (1 << (63 - 62)) /* Misaligned instruction (VLE) */
enum {
POWERPC_FLAG_NONE = 0x00000000,
diff --git a/target-ppc/helper.c b/target-ppc/helper.c
index 3abab1a..c23d4a4 100644
--- a/target-ppc/helper.c
+++ b/target-ppc/helper.c
@@ -1837,7 +1837,7 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong
address, int rw,
env->exception_index = POWERPC_EXCP_DTLB;
env->error_code = 0;
env->spr[SPR_BOOKE_DEAR] = address;
- env->spr[SPR_BOOKE_ESR] = rw ? 1 << ESR_ST : 0;
+ env->spr[SPR_BOOKE_ESR] = rw ? ESR_ST : 0;
return -1;
case POWERPC_MMU_REAL:
cpu_abort(env, "PowerPC in real mode should never raise "
@@ -1861,7 +1861,7 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong
address, int rw,
} else if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
(env->mmu_model == POWERPC_MMU_BOOKE206)) {
env->spr[SPR_BOOKE_DEAR] = address;
- env->spr[SPR_BOOKE_ESR] = rw ? 1 << ESR_ST : 0;
+ env->spr[SPR_BOOKE_ESR] = rw ? ESR_ST : 0;
} else {
env->spr[SPR_DAR] = address;
if (rw == 1) {
--
1.6.0.2