Re: [Qemu-devel] [PATCH] arm_gic: handle banked enable bits for per-cpu interrupts

[Peter Maydell]

On 28 October 2011 18:40, Rabin Vincent <address@hidden> wrote:
> The first enable set/clear register (which controls the PPIs and SGIs)
> is supposed to be banked for each processor.  Currently it is just
> handled globally and this prevents recent SMP Linux kernels from
> booting, because CPU0 stops receiving localtimer interrupts when CPU1
> disables them locally.
>
> To fix this, allow the enable bits to be enabled per-cpu.  For SPIs,
> always enable/disable ALL_CPU_MASK.

>  typedef struct gic_irq_state
>  {
> -    /* ??? The documentation seems to imply the enable bits are global, even
> -       for per-cpu interrupts.  This seems strange.  */
> -    unsigned enabled:1;
> +    /* The enable bits are only banked for per-cpu interrupts.  */
> +    unsigned enabled:NCPU;

The ??? comment here is referring to an ambiguity in the 11MPCore
TRM, which doesn't explicitly say that the enable bits for the
per-cpu interrupts are a banked register. (The GIC manual which
covers the A9 and up is clear here that they are banked.)

I have checked with real 11MPCore hardware, and the enable
register is banked between CPUs for the per-cpu interrupt,
so this patch is correct for 11MPCore as well as A9.

Incidentally, this code is shared with the M profile NVIC,
where the first enable register is not special at all. However
since M profile has only one core the special casing is harmless
and this patch only makes it match the other (pending etc)
registers, so I think that's OK.

Reviewed-by: Peter Maydell <address@hidden>

-- PMM