Re: [Qemu-devel] Patches for SMSC LAN911X driver

[Peter Maydell]

On 11 November 2011 13:44, Cachet Bertrand <address@hidden> wrote:
> In the driver for the SMSC LAN9118 device (hw/lan9118.c), I modify the code
> to update the PM_CTRL register (switch PM_MODE bits to D0 and set (1b) READY
> bit ) when writing to the BYTE_TEST register.

As Andreas says, if you can submit your patches in line with the
guidelines in http://wiki.qemu.org/Contribute/SubmitAPatch I'd
appreciate it. (In particular we can't apply any patch without a
Signed-off-by: line.)

On the meat of the patch:

   s->pmt_ctrl &= ~0x03000;
   s->pmt_ctrl |= 0x01;

At the moment these two lines will always have no effect, because
pmt_ctrl is set to 0x1 on initialisation and the register-writing
code never allows bits 0x3000 to be set or bit 0x1 to be cleared.

So I'm wondering if we should implement the other power modes
in a slightly more serious way. (Or perhaps we should just have
a comment that that code currently does nothing but is there
for if/when we do do the other power modes properly. Dunno.)

More generally, the data sheet is clear that "read only" means
"writes ignored" and "write only" means "reads as zero" so we
should make sure we implement that for all registers (not just
this one) rather than giving a hw_error().

-- PMM