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[Qemu-devel] [PATCH 4/5] Add dummy implementation of generic timer cp15
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 4/5] Add dummy implementation of generic timer cp15 registers |
Date: |
Wed, 25 Jan 2012 15:27:44 +0000 |
Add a dummy implementation of the cp15 registers for the generic
timer (found in the Cortex-A15), just sufficient for Linux to
decide that it can't use it. This requires at least CNTP_CTL and
CNTFRQ to be implemented as RAZ/WI; we RAZ/WI all of c14.
Reviewed-by: Andreas Färber <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu.h | 1 +
target-arm/helper.c | 12 ++++++++++--
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 42c53a7..7442c99 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -382,6 +382,7 @@ enum arm_features {
ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */
ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
+ ARM_FEATURE_GENERIC_TIMER,
};
static inline int arm_feature(CPUARMState *env, int feature)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 22e40fc..5e7205a 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1764,7 +1764,11 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn,
uint32_t val)
goto bad_reg;
}
break;
- case 14: /* Reserved. */
+ case 14: /* Generic timer */
+ if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
+ /* Dummy implementation: RAZ/WI for all */
+ break;
+ }
goto bad_reg;
case 15: /* Implementation specific. */
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
@@ -2134,7 +2138,11 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
default:
goto bad_reg;
}
- case 14: /* Reserved. */
+ case 14: /* Generic timer */
+ if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
+ /* Dummy implementation: RAZ/WI for all */
+ return 0;
+ }
goto bad_reg;
case 15: /* Implementation specific. */
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
--
1.7.1
- [Qemu-devel] [PULL 0/5] target-arm queue, Peter Maydell, 2012/01/25
- [Qemu-devel] [PATCH 1/5] target-arm: Fix implementation of TLB invalidate operations, Peter Maydell, 2012/01/25
- [Qemu-devel] [PATCH 2/5] target-arm/helper.c: Don't assume softfloat int32 is 32 bits only, Peter Maydell, 2012/01/25
- [Qemu-devel] [PATCH 3/5] arm: store the config_base_register during cpu_reset, Peter Maydell, 2012/01/25
- [Qemu-devel] [PATCH 4/5] Add dummy implementation of generic timer cp15 registers,
Peter Maydell <=
- [Qemu-devel] [PATCH 5/5] Add Cortex-A15 CPU definition, Peter Maydell, 2012/01/25
- Re: [Qemu-devel] [PULL 0/5] target-arm queue, Blue Swirl, 2012/01/28