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Re: [Qemu-devel] IRQ number, interrupt number, interrupt line & GPIO[in/
From: |
Zhi Yong Wu |
Subject: |
Re: [Qemu-devel] IRQ number, interrupt number, interrupt line & GPIO[in/out] |
Date: |
Sat, 3 Mar 2012 10:06:00 +0800 |
HI, anthony.
On Sat, Mar 3, 2012 at 12:01 AM, Anthony Liguori <address@hidden> wrote:
> Hi Zhi Yong,
>
>
> On 03/02/2012 06:38 AM, Zhi Yong Wu wrote:
>>
>> HI,
>>
>> Can anyone explain their relationship and difference among them? It
>> is very appreciated if you can make some comments. thanks.
>
>
> IRQ == interrupt.
>
> GPIO is just another name for an input or output pin on a chip which could
> be a IRQ line.
>
> Interrupt controllers can receive interrupts from one or more devices.
> Usually, the input pins on an interrupt controller can be numbered
> sequentially. When we say that the first UART is on IRQ number 3, what that
> really means is that the IRQ output pin on the UART chip is connected to pin
> number 3 on the interrupt controller with a wire.
>
> But there never is a single interrupt controller in a real system. For
> instance, a PCI bus has it's own interrupt controller that has four input
> pins (called LNKs) that are oddly labeled A, B, C, D.
thanks, i got what they mean.
>
> For the I440FX PCI bus, those four input pins are mapped to two IRQs which
> are then connected to the I/O APIC.
What do two IRQs mean here? how will those four input pins be mapped
to two IRQs? For example, 8259 interrupt controller is connected to
I/O APIC.
How will these two IRQs be connected to I/O APIC? i think that those
four input pins are connected to I/O APIC with wire, right?
Can you elaborate them if you are available?
>
> Regards,
>
> Anthony Liguori
--
Regards,
Zhi Yong Wu