Re: [Qemu-devel] [PATCH] Fix typo in i400FX chipset init code

[Alexey Korolev]

> On Wed, Feb 29, 2012 at 02:35:14PM +1300, Alexey Korolev wrote:
> I've fixed the commit message and applied. 
Thank you!
> How does one trigger the problem?
> I'd like to know so I can test for it.

The i440fx_init() function is called from pc_init code.
The call looks like that:
pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, &isa_bus, gsi,
                               system_memory, system_io, ram_size,
<http://git.kernel.org/?p=virt/kvm/qemu-kvm.git;a=blob;f=hw/pc_piix.c;hb=a27726650ecc89b4a518a9a5d256de852894b3a2#l200>
                              
below_4g_mem_size,
<http://git.kernel.org/?p=virt/kvm/qemu-kvm.git;a=blob;f=hw/pc_piix.c;hb=a27726650ecc89b4a518a9a5d256de852894b3a2#l201>
                              
0x100000000ULL - below_4g_mem_size,
<http://git.kernel.org/?p=virt/kvm/qemu-kvm.git;a=blob;f=hw/pc_piix.c;hb=a27726650ecc89b4a518a9a5d256de852894b3a2#l202>
                              
0x100000000ULL + above_4g_mem_size,
<http://git.kernel.org/?p=virt/kvm/qemu-kvm.git;a=blob;f=hw/pc_piix.c;hb=a27726650ecc89b4a518a9a5d256de852894b3a2#l203>
                              
(sizeof(target_phys_addr_t) == 4
<http://git.kernel.org/?p=virt/kvm/qemu-kvm.git;a=blob;f=hw/pc_piix.c;hb=a27726650ecc89b4a518a9a5d256de852894b3a2#l204>
                               
? 0
<http://git.kernel.org/?p=virt/kvm/qemu-kvm.git;a=blob;f=hw/pc_piix.c;hb=a27726650ecc89b4a518a9a5d256de852894b3a2#l205>
                               
: ((uint64_t)1 << 62)),
<http://git.kernel.org/?p=virt/kvm/qemu-kvm.git;a=blob;f=hw/pc_piix.c;hb=a27726650ecc89b4a518a9a5d256de852894b3a2#l206>
                              
pci_memory, ram_memory);

So we have

pci_hole64_size = 1 << 62

and because of typo  we also have 

pci_hole64_start = 1 << 62

The pci_hole64_start & pci_hole64_size are used to build memory regions access 
ranges.
Since 64bit PCI regions must be below 1<<40 and pci_hole64_start is 1 << 62, we 
have situations when all
64bit PCI regions are inaccessible.

For how to test it:
Convert device to use 64bit PCI BARs (ivshmem.c for example).
Apply patches for 64 bit support in seabios:
http://lists.nongnu.org/archive/html/qemu-devel/2012-03/msg00018.html.

Try to access the content of 64bit PCI memory. It will fail!


P/s:
IMHO it makes sence to update pc_iix.c code as well.
The pci_hole64_size value is incorrect anyway.


>> ---
>>
>>  hw/piix_pci.c |    2 +-
>>  1 files changed, 1 insertions(+), 1 deletions(-)
>>
>> diff --git a/hw/piix_pci.c b/hw/piix_pci.c
>> index 3ed3d90..aab8188 100644
>> --- a/hw/piix_pci.c
>> +++ b/hw/piix_pci.c
>> @@ -353,7 +353,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int 
>> *piix3_devfn,
>>      b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, isa_bus, 
>> pic,
>>                             address_space_mem, address_space_io, ram_size,
>>                             pci_hole_start, pci_hole_size,
>> -                           pci_hole64_size, pci_hole64_size,
>> +                           pci_hole64_start, pci_hole64_size,
>>                             pci_memory, ram_memory);
>>      return b;
>>  }
>>
>>
>>
>>