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[Qemu-devel] [PATCH 11/14] tcg-sparc: Mask shift immediates to avoid ill
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 11/14] tcg-sparc: Mask shift immediates to avoid illegal insns. |
Date: |
Tue, 27 Mar 2012 17:32:20 -0700 |
The xtensa-test image generates a sra_i32 with count 0x40.
Whether this is accident of tcg constant propagation or
originating directly from the instruction stream is immaterial.
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/sparc/tcg-target.c | 18 ++++++++++++------
1 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index 88c5140..5b3cde4 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -1184,13 +1184,16 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc, const TCGArg *args,
goto gen_arith;
case INDEX_op_shl_i32:
c = SHIFT_SLL;
- goto gen_arith;
+ do_shift32:
+ /* Limit immediate shift count lest we create an illegal insn. */
+ tcg_out_arithc(s, args[0], args[1], args[2] & 31, const_args[2], c);
+ break;
case INDEX_op_shr_i32:
c = SHIFT_SRL;
- goto gen_arith;
+ goto do_shift32;
case INDEX_op_sar_i32:
c = SHIFT_SRA;
- goto gen_arith;
+ goto do_shift32;
case INDEX_op_mul_i32:
c = ARITH_UMUL;
goto gen_arith;
@@ -1311,13 +1314,16 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc, const TCGArg *args,
break;
case INDEX_op_shl_i64:
c = SHIFT_SLLX;
- goto gen_arith;
+ do_shift64:
+ /* Limit immediate shift count lest we create an illegal insn. */
+ tcg_out_arithc(s, args[0], args[1], args[2] & 63, const_args[2], c);
+ break;
case INDEX_op_shr_i64:
c = SHIFT_SRLX;
- goto gen_arith;
+ goto do_shift64;
case INDEX_op_sar_i64:
c = SHIFT_SRAX;
- goto gen_arith;
+ goto do_shift64;
case INDEX_op_mul_i64:
c = ARITH_MULX;
goto gen_arith;
--
1.7.7.6
- Re: [Qemu-devel] [PATCH 03/14] tcg-sparc: Assume v9 cpu always, i.e. force v8plus in 32-bit mode., (continued)
- [Qemu-devel] [PATCH 06/14] tcg-sparc: Support GUEST_BASE., Richard Henderson, 2012/03/27
- [Qemu-devel] [PATCH 04/14] tcg-sparc: Fix qemu_ld/st to handle 32-bit host., Richard Henderson, 2012/03/27
- [Qemu-devel] [PATCH 07/14] Avoid declaring the env variable at all if CONFIG_TCG_PASS_AREG0., Richard Henderson, 2012/03/27
- [Qemu-devel] [PATCH 09/14] tcg-sparc: Change AREG0 in generated code to %i0., Richard Henderson, 2012/03/27
- [Qemu-devel] [PATCH 05/14] tcg-sparc: Simplify qemu_ld/st direct memory paths., Richard Henderson, 2012/03/27
- [Qemu-devel] [PATCH 08/14] tcg-sparc: Do not use a global register for AREG0., Richard Henderson, 2012/03/27
- [Qemu-devel] [PATCH 10/14] tcg-sparc: Clean up cruft stemming from attempts to use global registers., Richard Henderson, 2012/03/27
- [Qemu-devel] [PATCH 11/14] tcg-sparc: Mask shift immediates to avoid illegal insns.,
Richard Henderson <=
- [Qemu-devel] [PATCH 14/14] tcg-sparc: Fix and enable direct TB chaining., Richard Henderson, 2012/03/27
- [Qemu-devel] [PATCH 12/14] tcg-sparc: Use defines for temporaries., Richard Henderson, 2012/03/27
- [Qemu-devel] [PATCH 13/14] tcg-sparc: Add %g/%o registers to alloc_order, Richard Henderson, 2012/03/27