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[Qemu-devel] [PATCH V4 02/11] Use correct acc value to index cpu_HI/cpu_
From: |
Jia Liu |
Subject: |
[Qemu-devel] [PATCH V4 02/11] Use correct acc value to index cpu_HI/cpu_LO rather than using a fix number |
Date: |
Fri, 30 Mar 2012 11:17:03 +0800 |
There are 4 accumulator registers (acc) used by MIPS ASE DSP instructions.
Each accumulator register is composed of by HIGH and LOW part. Use correct
acc value to index cpu_HI/cpu_LO rather than using a fix number (i.e. zero).
Signed-off-by: Jia Liu <address@hidden>
---
target-mips/translate.c | 56 ++++++++++++++++++++++++++++------------------
1 files changed, 34 insertions(+), 22 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index a663b74..f869146 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1972,6 +1972,7 @@ static void gen_shift (CPUMIPSState *env, DisasContext
*ctx, uint32_t opc,
static void gen_HILO (DisasContext *ctx, uint32_t opc, int reg)
{
const char *opn = "hilo";
+ unsigned int acc;
if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) {
/* Treat as NOP. */
@@ -1980,25 +1981,29 @@ static void gen_HILO (DisasContext *ctx, uint32_t opc,
int reg)
}
switch (opc) {
case OPC_MFHI:
- tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[0]);
+ acc = ((ctx->opcode) >> 21) & 0x03;
+ tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[acc]);
opn = "mfhi";
break;
case OPC_MFLO:
- tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[0]);
+ acc = ((ctx->opcode) >> 21) & 0x03;
+ tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[acc]);
opn = "mflo";
break;
case OPC_MTHI:
+ acc = ((ctx->opcode) >> 11) & 0x03;
if (reg != 0)
- tcg_gen_mov_tl(cpu_HI[0], cpu_gpr[reg]);
+ tcg_gen_mov_tl(cpu_HI[acc], cpu_gpr[reg]);
else
- tcg_gen_movi_tl(cpu_HI[0], 0);
+ tcg_gen_movi_tl(cpu_HI[acc], 0);
opn = "mthi";
break;
case OPC_MTLO:
+ acc = ((ctx->opcode) >> 11) & 0x03;
if (reg != 0)
- tcg_gen_mov_tl(cpu_LO[0], cpu_gpr[reg]);
+ tcg_gen_mov_tl(cpu_LO[acc], cpu_gpr[reg]);
else
- tcg_gen_movi_tl(cpu_LO[0], 0);
+ tcg_gen_movi_tl(cpu_LO[acc], 0);
opn = "mtlo";
break;
}
@@ -2011,6 +2016,7 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
{
const char *opn = "mul/div";
TCGv t0, t1;
+ unsigned int acc;
switch (opc) {
case OPC_DIV:
@@ -2073,6 +2079,7 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
{
TCGv_i64 t2 = tcg_temp_new_i64();
TCGv_i64 t3 = tcg_temp_new_i64();
+ acc = (ctx->opcode >> 11) & 0x03;
tcg_gen_ext_tl_i64(t2, t0);
tcg_gen_ext_tl_i64(t3, t1);
@@ -2082,8 +2089,8 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
tcg_gen_shri_i64(t2, t2, 32);
tcg_gen_trunc_i64_tl(t1, t2);
tcg_temp_free_i64(t2);
- tcg_gen_ext32s_tl(cpu_LO[0], t0);
- tcg_gen_ext32s_tl(cpu_HI[0], t1);
+ tcg_gen_ext32s_tl(cpu_LO[acc], t0);
+ tcg_gen_ext32s_tl(cpu_HI[acc], t1);
}
opn = "mult";
break;
@@ -2091,6 +2098,7 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
{
TCGv_i64 t2 = tcg_temp_new_i64();
TCGv_i64 t3 = tcg_temp_new_i64();
+ acc = (ctx->opcode >> 11) & 0x03;
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_ext32u_tl(t1, t1);
@@ -2102,8 +2110,8 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
tcg_gen_shri_i64(t2, t2, 32);
tcg_gen_trunc_i64_tl(t1, t2);
tcg_temp_free_i64(t2);
- tcg_gen_ext32s_tl(cpu_LO[0], t0);
- tcg_gen_ext32s_tl(cpu_HI[0], t1);
+ tcg_gen_ext32s_tl(cpu_LO[acc], t0);
+ tcg_gen_ext32s_tl(cpu_HI[acc], t1);
}
opn = "multu";
break;
@@ -2150,19 +2158,20 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
{
TCGv_i64 t2 = tcg_temp_new_i64();
TCGv_i64 t3 = tcg_temp_new_i64();
+ acc = (ctx->opcode >> 11) & 0x03;
tcg_gen_ext_tl_i64(t2, t0);
tcg_gen_ext_tl_i64(t3, t1);
tcg_gen_mul_i64(t2, t2, t3);
- tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]);
+ tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
tcg_gen_add_i64(t2, t2, t3);
tcg_temp_free_i64(t3);
tcg_gen_trunc_i64_tl(t0, t2);
tcg_gen_shri_i64(t2, t2, 32);
tcg_gen_trunc_i64_tl(t1, t2);
tcg_temp_free_i64(t2);
- tcg_gen_ext32s_tl(cpu_LO[0], t0);
- tcg_gen_ext32s_tl(cpu_HI[0], t1);
+ tcg_gen_ext32s_tl(cpu_LO[acc], t0);
+ tcg_gen_ext32s_tl(cpu_HI[acc], t1);
}
opn = "madd";
break;
@@ -2170,21 +2179,22 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
{
TCGv_i64 t2 = tcg_temp_new_i64();
TCGv_i64 t3 = tcg_temp_new_i64();
+ acc = (ctx->opcode >> 11) & 0x03;
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_ext32u_tl(t1, t1);
tcg_gen_extu_tl_i64(t2, t0);
tcg_gen_extu_tl_i64(t3, t1);
tcg_gen_mul_i64(t2, t2, t3);
- tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]);
+ tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
tcg_gen_add_i64(t2, t2, t3);
tcg_temp_free_i64(t3);
tcg_gen_trunc_i64_tl(t0, t2);
tcg_gen_shri_i64(t2, t2, 32);
tcg_gen_trunc_i64_tl(t1, t2);
tcg_temp_free_i64(t2);
- tcg_gen_ext32s_tl(cpu_LO[0], t0);
- tcg_gen_ext32s_tl(cpu_HI[0], t1);
+ tcg_gen_ext32s_tl(cpu_LO[acc], t0);
+ tcg_gen_ext32s_tl(cpu_HI[acc], t1);
}
opn = "maddu";
break;
@@ -2192,19 +2202,20 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
{
TCGv_i64 t2 = tcg_temp_new_i64();
TCGv_i64 t3 = tcg_temp_new_i64();
+ acc = (ctx->opcode >> 11) & 0x03;
tcg_gen_ext_tl_i64(t2, t0);
tcg_gen_ext_tl_i64(t3, t1);
tcg_gen_mul_i64(t2, t2, t3);
- tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]);
+ tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
tcg_gen_sub_i64(t2, t3, t2);
tcg_temp_free_i64(t3);
tcg_gen_trunc_i64_tl(t0, t2);
tcg_gen_shri_i64(t2, t2, 32);
tcg_gen_trunc_i64_tl(t1, t2);
tcg_temp_free_i64(t2);
- tcg_gen_ext32s_tl(cpu_LO[0], t0);
- tcg_gen_ext32s_tl(cpu_HI[0], t1);
+ tcg_gen_ext32s_tl(cpu_LO[acc], t0);
+ tcg_gen_ext32s_tl(cpu_HI[acc], t1);
}
opn = "msub";
break;
@@ -2212,21 +2223,22 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
{
TCGv_i64 t2 = tcg_temp_new_i64();
TCGv_i64 t3 = tcg_temp_new_i64();
+ acc = (ctx->opcode >> 11) & 0x03;
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_ext32u_tl(t1, t1);
tcg_gen_extu_tl_i64(t2, t0);
tcg_gen_extu_tl_i64(t3, t1);
tcg_gen_mul_i64(t2, t2, t3);
- tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]);
+ tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
tcg_gen_sub_i64(t2, t3, t2);
tcg_temp_free_i64(t3);
tcg_gen_trunc_i64_tl(t0, t2);
tcg_gen_shri_i64(t2, t2, 32);
tcg_gen_trunc_i64_tl(t1, t2);
tcg_temp_free_i64(t2);
- tcg_gen_ext32s_tl(cpu_LO[0], t0);
- tcg_gen_ext32s_tl(cpu_HI[0], t1);
+ tcg_gen_ext32s_tl(cpu_LO[acc], t0);
+ tcg_gen_ext32s_tl(cpu_HI[acc], t1);
}
opn = "msubu";
break;
--
1.7.5.4
- [Qemu-devel] [PATCH V4 00/11] Qemu MIPS ASE DSP Sup port, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 01/11] Add MIPS DSP internal functions, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 02/11] Use correct acc value to index cpu_HI/cpu_LO rather than using a fix number,
Jia Liu <=
- [Qemu-devel] [PATCH V4 03/11] Add MIPS DSP Branch instruction Support, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 04/11] Add MIPS DSP Load instructions Support, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 05/11] Add MIPS DSP Arithmetic instructions Support, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 06/11] Add MIPS DSP GPR-Based Shift instructions Support, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 07/11] Add MIPS DSP Multiply instructions Support, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 08/11] Add MIPS DSP Bit/Manipulation instructions Support, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 09/11] Add MIPS DSP Compare-Pick instructions Support, Jia Liu, 2012/03/29