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[Qemu-devel] [PATCH 03/14] target-arm: Move FPSID config to cpu init fns
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 03/14] target-arm: Move FPSID config to cpu init fns |
Date: |
Fri, 30 Mar 2012 13:51:39 +0100 |
Move the reset FPSID to the ARMCPU struct, and set it in the
per-implementation instance init function. At reset we then
just copy the reset value into the CPUARMState field.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu-qom.h | 1 +
target-arm/cpu.c | 9 +++++++++
target-arm/helper.c | 10 ++--------
3 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 1a3965f..a842917 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -63,6 +63,7 @@ typedef struct ARMCPU {
* some of these might become properties eventually.
*/
uint32_t midr;
+ uint32_t reset_fpsid;
} ARMCPU;
static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 0dad352..2b881ac 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -103,6 +103,7 @@ static void arm926_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V5);
set_feature(&cpu->env, ARM_FEATURE_VFP);
cpu->midr = ARM_CPUID_ARM926;
+ cpu->reset_fpsid = 0x41011090;
arm_cpu_postconfig_init(cpu);
}
@@ -122,6 +123,7 @@ static void arm1026_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_VFP);
set_feature(&cpu->env, ARM_FEATURE_AUXCR);
cpu->midr = ARM_CPUID_ARM1026;
+ cpu->reset_fpsid = 0x410110a0;
arm_cpu_postconfig_init(cpu);
}
@@ -131,6 +133,7 @@ static void arm1136_r2_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V6);
set_feature(&cpu->env, ARM_FEATURE_VFP);
cpu->midr = ARM_CPUID_ARM1136_R2;
+ cpu->reset_fpsid = 0x410120b4;
arm_cpu_postconfig_init(cpu);
}
@@ -141,6 +144,7 @@ static void arm1136_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V6);
set_feature(&cpu->env, ARM_FEATURE_VFP);
cpu->midr = ARM_CPUID_ARM1136;
+ cpu->reset_fpsid = 0x410120b4;
arm_cpu_postconfig_init(cpu);
}
@@ -151,6 +155,7 @@ static void arm1176_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_VFP);
set_feature(&cpu->env, ARM_FEATURE_VAPA);
cpu->midr = ARM_CPUID_ARM1176;
+ cpu->reset_fpsid = 0x410120b5;
arm_cpu_postconfig_init(cpu);
}
@@ -161,6 +166,7 @@ static void arm11mpcore_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_VFP);
set_feature(&cpu->env, ARM_FEATURE_VAPA);
cpu->midr = ARM_CPUID_ARM11MPCORE;
+ cpu->reset_fpsid = 0x410120b4;
arm_cpu_postconfig_init(cpu);
}
@@ -181,6 +187,7 @@ static void cortex_a8_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
cpu->midr = ARM_CPUID_CORTEXA8;
+ cpu->reset_fpsid = 0x410330c0;
arm_cpu_postconfig_init(cpu);
}
@@ -198,6 +205,7 @@ static void cortex_a9_initfn(Object *obj)
*/
set_feature(&cpu->env, ARM_FEATURE_V7MP);
cpu->midr = ARM_CPUID_CORTEXA9;
+ cpu->reset_fpsid = 0x41033090;
arm_cpu_postconfig_init(cpu);
}
@@ -213,6 +221,7 @@ static void cortex_a15_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V7MP);
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
cpu->midr = ARM_CPUID_CORTEXA15;
+ cpu->reset_fpsid = 0x410430f0;
arm_cpu_postconfig_init(cpu);
}
diff --git a/target-arm/helper.c b/target-arm/helper.c
index af752e4..c7cde4f 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -51,7 +51,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
{
switch (id) {
case ARM_CPUID_ARM926:
- env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00090078;
break;
@@ -60,7 +59,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00000078;
break;
case ARM_CPUID_ARM1026:
- env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00090078;
break;
@@ -75,7 +73,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
* for 1136_r2 (in particular r0p2 does not actually implement most
* of the ID registers).
*/
- env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
@@ -84,7 +81,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00050078;
break;
case ARM_CPUID_ARM1176:
- env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b5;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
memcpy(env->cp15.c0_c1, arm1176_cp15_c0_c1, 8 * sizeof(uint32_t));
@@ -93,7 +89,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00050078;
break;
case ARM_CPUID_ARM11MPCORE:
- env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t));
@@ -101,7 +96,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c0_cachetype = 0x1dd20d2;
break;
case ARM_CPUID_CORTEXA8:
- env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
@@ -114,7 +108,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t
id)
env->cp15.c1_sys = 0x00c50078;
break;
case ARM_CPUID_CORTEXA9:
- env->vfp.xregs[ARM_VFP_FPSID] = 0x41033090;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t));
@@ -126,7 +119,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t
id)
env->cp15.c1_sys = 0x00c50078;
break;
case ARM_CPUID_CORTEXA15:
- env->vfp.xregs[ARM_VFP_FPSID] = 0x410430f0;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x10110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x11111111;
memcpy(env->cp15.c0_c1, cortexa15_cp15_c0_c1, 8 * sizeof(uint32_t));
@@ -202,6 +194,8 @@ void cpu_state_reset(CPUARMState *env)
cpu_reset_model_id(env, id);
env->cp15.c15_config_base_address = tmp;
env->cp15.c0_cpuid = cpu->midr;
+ env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
+
#if defined (CONFIG_USER_ONLY)
env->uncached_cpsr = ARM_CPU_MODE_USR;
/* For user mode we must enable access to coprocessors */
--
1.7.1
- [Qemu-devel] [PATCH 08/14] target-arm: Move iWMMXT wCID reset to cpu_state_reset, (continued)
- [Qemu-devel] [PATCH 08/14] target-arm: Move iWMMXT wCID reset to cpu_state_reset, Peter Maydell, 2012/03/30
- [Qemu-devel] [PATCH 10/14] target-arm: Move OMAP cp15_i_{max, min} reset to cpu_state_reset, Peter Maydell, 2012/03/30
- [Qemu-devel] [PATCH 12/14] target-arm: Drop cpu_reset_model_id(), Peter Maydell, 2012/03/30
- [Qemu-devel] [PATCH 14/14] target-arm: Move A9 config_base_address reset value to ARMCPU, Peter Maydell, 2012/03/30
- [Qemu-devel] [PATCH 04/14] target-arm: Move MVFR* setup to per cpu init fns, Peter Maydell, 2012/03/30
- [Qemu-devel] [PATCH 02/14] target-arm: Move feature bit settings to CPU init fns, Peter Maydell, 2012/03/30
- [Qemu-devel] [PATCH 06/14] target-arm: Move SCTLR reset value setup to per cpu init fns, Peter Maydell, 2012/03/30
- [Qemu-devel] [PATCH 05/14] target-arm: Move CTR setup to per cpu init fns, Peter Maydell, 2012/03/30
- [Qemu-devel] [PATCH 03/14] target-arm: Move FPSID config to cpu init fns,
Peter Maydell <=