Re: [Qemu-devel] [Qemu-ppc] [PATCHv3] PPC: Fix interrupt MSR value for classic exception models.

[David Gibson]

On Fri, Apr 06, 2012 at 08:06:27PM +0100, Mark Cave-Ayland wrote:
> Commit 41557447d30eeb944e42069513df13585f5e6c7f introduced a new method of
> calculating the MSR for the interrupt context. However this doesn't quite
> agree with the PowerISA 2.06B specification (pp. 811-814) since too many
> bits were being cleared.
> 
> This patch corrects the calculation of the interrupt MSR for classic exception
> models whilst including additional comments to clarify which bits are being
> changed within both the MSR and the interrupt MSR.
> 
> Signed-off-by: Mark Cave-Ayland <address@hidden>
> Signed-off-by: Martin Sucha <address@hidden>
> ---
>  target-ppc/cpu.h    |    2 ++
>  target-ppc/helper.c |   31 ++++++++++++++++++++++++++++---
>  2 files changed, 30 insertions(+), 3 deletions(-)
> 
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index ca6f1cb..9a1c493 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -428,6 +428,8 @@ struct ppc_slb_t {
>  
>  
> /*****************************************************************************/
>  /* Machine state register bits definition                                    
> */
> +#define MSR_BIT(x) ((target_ulong)1 << MSR_##x)
> +
>  #define MSR_SF   63 /* Sixty-four-bit mode                            hflags 
> */
>  #define MSR_TAG  62 /* Tag-active mode (POWERx ?)                            
> */
>  #define MSR_ISF  61 /* Sixty-four-bit interrupt mode on 630                  
> */
> diff --git a/target-ppc/helper.c b/target-ppc/helper.c
> index 63a0dec..99beace 100644
> --- a/target-ppc/helper.c
> +++ b/target-ppc/helper.c
> @@ -2478,11 +2478,36 @@ static inline void powerpc_excp(CPUPPCState *env, int 
> excp_model, int excp)
>      qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
>                    " => %08x (%02x)\n", env->nip, excp, env->error_code);
>  
> -    /* new srr1 value excluding must-be-zero bits */
> +    /* new srr1 value with interrupt-specific bits defaulting to zero */
>      msr = env->msr & ~0x783f0000ULL;

Sorry, I really should have picked this up in an earlier review round,
but I think the *whole* msr calculation should be made per exception
model, not just the second part.  The common statement above
is.. cryptic, and I'd be mildly surprised if it was correct for all
architected variants.

> -    /* new interrupt handler msr */
> -    new_msr = env->msr & ((target_ulong)1 << MSR_ME);
> +    switch (excp_model) {
> +    case POWERPC_EXCP_STD:
> +    case POWERPC_EXCP_601:
> +    case POWERPC_EXCP_602:
> +    case POWERPC_EXCP_603:
> +    case POWERPC_EXCP_603E:
> +    case POWERPC_EXCP_604:
> +    case POWERPC_EXCP_7x0:
> +    case POWERPC_EXCP_7x5:
> +    case POWERPC_EXCP_74xx:
> +    case POWERPC_EXCP_G2: 
> +        /* new classic interrupt handler msr (as per PowerISA 2.06B p.811 
> and 
> +           p.814): 
> +           1) force the following bits to zero
> +              IR, DR, FE0, FE1, EE, BE, FP, PMM, PR, SE
> +           2) default the following bits to zero (can be overidden later on)
> +              POW, RI */
> +        new_msr = env->msr & ~(MSR_BIT(IR) | MSR_BIT(DR) | MSR_BIT(FE0)
> +                      | MSR_BIT(FE1) | MSR_BIT(EE) | MSR_BIT(BE) | 
> MSR_BIT(FP)
> +                      | MSR_BIT(PMM) | MSR_BIT(PR) | MSR_BIT(SE) | 
> MSR_BIT(POW)
> +                      | MSR_BIT(RI));
> +        break;
> +    default:
> +        /* new interrupt handler msr */
> +        new_msr = env->msr & ((target_ulong)1 << MSR_ME);
> +        break;
> +   }
>  
>      /* target registers */
>      srr0 = SPR_SRR0;

-- 
David Gibson                    | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
                                | _way_ _around_!
http://www.ozlabs.org/~dgibson