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[Qemu-devel] [PATCH v2 10/17] Openrisc: add Programmable Interrupt Contr
From: |
Jia Liu |
Subject: |
[Qemu-devel] [PATCH v2 10/17] Openrisc: add Programmable Interrupt Controller |
Date: |
Sun, 27 May 2012 13:32:52 +0800 |
add Programmable Interrupt Controller for openrisc.
Signed-off-by: Jia Liu <address@hidden>
---
hw/openrisc_pic.c | 50 +++++++++++++++++++++++++++++++++++++++++++++++++
target-openrisc/cpu.h | 5 +++++
2 files changed, 55 insertions(+)
diff --git a/hw/openrisc_pic.c b/hw/openrisc_pic.c
index 201c6bc..1c28904 100644
--- a/hw/openrisc_pic.c
+++ b/hw/openrisc_pic.c
@@ -25,4 +25,54 @@
/* Reset PIC */
void cpu_openrisc_pic_reset(CPUOpenriscState *env)
{
+ env->picmr = 0x00000000;
+ env->picsr = 0x00000000;
+}
+
+/* openrisc pic handler */
+static void openrisc_pic_cpu_handler(void *opaque, int irq, int level)
+{
+ CPUOpenriscState *env = (CPUOpenriscState *)opaque;
+ int i;
+ uint32_t irq_bit = 1 << irq;
+
+ if (irq > 31 || irq < 0) {
+ return;
+ }
+
+ if (level) {
+ env->picsr |= irq_bit;
+ } else {
+ env->picsr &= ~irq_bit;
+ }
+
+ for (i = 0; i < 32; i++) {
+ if ((env->picsr && (1 << i)) && (env->picmr && (1 << i))) {
+ cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ } else {
+ cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+ env->picsr &= ~(1 << i);
+ }
+ }
+}
+
+void cpu_openrisc_pic_init(CPUOpenriscState *env)
+{
+ int i;
+ qemu_irq *qi;
+ qi = qemu_allocate_irqs(openrisc_pic_cpu_handler, env, NR_IRQS);
+
+ for (i = 0; i < NR_IRQS; i++) {
+ env->irq[i] = qi[i];
+ }
+}
+
+void cpu_openrisc_store_picmr(CPUOpenriscState *env, uint32_t value)
+{
+ env->picmr |= value;
+}
+
+void cpu_openrisc_store_picsr(CPUOpenriscState *env, uint32_t value)
+{
+ env->picsr &= ~value;
}
diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
index 0f332ab..7417dcc 100644
--- a/target-openrisc/cpu.h
+++ b/target-openrisc/cpu.h
@@ -198,6 +198,9 @@ struct CPUOpenriscState {
int (*map_address_data)(struct CPUOpenriscState *env,
target_phys_addr_t *physical, int *prot,
target_ulong address, int rw);
+
+ uint32_t picmr; /* Interrupt mask register */
+ uint32_t picsr; /* Interrupt contrl register*/
#endif
uint32_t fpcsr; /* Float register */
float_status fp_status;
@@ -274,6 +277,8 @@ int cpu_openrisc_handle_mmu_fault(CPUOpenriscState *env,
target_ulong address,
void openrisc_reset(CPUOpenriscState *env);
#if !defined(CONFIG_USER_ONLY)
void cpu_openrisc_pic_reset(CPUOpenriscState *env);
+void cpu_openrisc_store_picsr(CPUOpenriscState *env, uint32_t value);
+void cpu_openrisc_store_picmr(CPUOpenriscState *env, uint32_t value);
void openrisc_mmu_init(CPUOpenriscState *env);
int get_phys_nommu(CPUOpenriscState *env, target_phys_addr_t *physical,
--
1.7.9.5
- Re: [Qemu-devel] [PATCH v2 01/17] Openrisc: add target stubs, (continued)
- [Qemu-devel] [PATCH v2 02/17] Openrisc: add cpu QOM implement, Jia Liu, 2012/05/27
- [Qemu-devel] [PATCH v2 03/17] Openrisc: add basic machine, Jia Liu, 2012/05/27
- [Qemu-devel] [PATCH v2 04/17] Openrisc: add MMU support, Jia Liu, 2012/05/27
- [Qemu-devel] [PATCH v2 06/17] Openrisc: add exception support, Jia Liu, 2012/05/27
- [Qemu-devel] [PATCH v2 07/17] Openrisc: add int instruction helpers, Jia Liu, 2012/05/27
- [Qemu-devel] [PATCH v2 08/17] Openrisc: add float instruction helpers, Jia Liu, 2012/05/27
- [Qemu-devel] [PATCH v2 09/17] Openrisc: add instruction translation routines, Jia Liu, 2012/05/27
- [Qemu-devel] [PATCH v2 10/17] Openrisc: add Programmable Interrupt Controller,
Jia Liu <=
- [Qemu-devel] [PATCH v2 11/17] Openrisc: add a timer, Jia Liu, 2012/05/27
- [Qemu-devel] [PATCH v2 12/17] Openrisc: add a simulator board, Jia Liu, 2012/05/27
- [Qemu-devel] [PATCH v2 13/17] Openrisc: add system instruction helpers, Jia Liu, 2012/05/27
- [Qemu-devel] [PATCH v2 14/17] Openrisc: add gdb stub support, Jia Liu, 2012/05/27
- [Qemu-devel] [PATCH v2 16/17] Openrisc: add linux user support, Jia Liu, 2012/05/27
- [Qemu-devel] [PATCH v2 17/17] Openrisc: add testcases, Jia Liu, 2012/05/27
- [Qemu-devel] [PATCH v2 15/17] Openrisc: add linux syscall, signal and termbits, Jia Liu, 2012/05/27
- Re: [Qemu-devel] [PATCH v2 00/17] Qemu Openrisc support, Stefan Weil, 2012/05/27
- [Qemu-devel] [PATCH v2 05/17] Openrisc: add interrupt support, Jia Liu, 2012/05/27