Re: [Qemu-devel] [PATCH v6 08/16] target-or32: Add instruction tanslation

[Jia Liu]

Hi Max,

On Thu, Jun 21, 2012 at 6:24 PM, Max Filippov <address@hidden> wrote:
> On Thu, Jun 21, 2012 at 6:58 AM, Jia Liu <address@hidden> wrote:
>> Add OpenRISC instruction tanslation routines.
>>
>> Signed-off-by: Jia Liu <address@hidden>
>
> [...]
>
>> +    case 0x0009:
>> +        switch (op1) {
>> +        case 0x03:   /*l.div*/
>> +            LOG_DIS("l.div r%d, r%d, r%d\n", rd, ra, rb);
>> +            {
>> +                int lab0 = gen_new_label();
>> +                int lab1 = gen_new_label();
>> +                int lab2 = gen_new_label();
>> +                TCGv_i32 sr_ove = tcg_temp_local_new_i32();
>> +                if (rb == 0) {
>> +                    tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
>> +                    tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab0);
>> +                    tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE);
>> +                    gen_exception(dc, EXCP_RANGE);
>> +                    gen_set_label(lab0);
>> +                } else {
>> +                    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_R[rb],
>> +                                       0x00000000, lab1);
>> +                    tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[ra],
>> +                                       0xffffffff, lab2);
>> +                    tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[rb],
>> +                                       0x80000000, lab2);
>> +                    gen_set_label(lab1);
>> +                    tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
>> +                    tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE);
>> +                    tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab2);
>
> Causes host division by zero/overflow. I'd suggest to brcond to lab3 set after
> the final tcg_gen_div.

Causes host division by zero/overflow? Can I handle the host code? I'm
confused about this.
May I get more comment about this? Sorry I didn't understand it.

>
>> +                    gen_exception(dc, EXCP_RANGE);
>> +                    gen_set_label(lab2);
>> +                    tcg_gen_div_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
>> +                }
>> +                tcg_temp_free_i32(sr_ove);
>> +            }
>> +            break;
>> +
>> +        default:
>> +            gen_illegal_exception(dc);
>> +            break;
>> +        }
>> +        break;
>> +
>> +    case 0x000a:
>> +        switch (op1) {
>> +        case 0x03:   /*l.divu*/
>> +            LOG_DIS("l.divu r%d, r%d, r%d\n", rd, ra, rb);
>> +            {
>> +                int lab0 = gen_new_label();
>> +                int lab1 = gen_new_label();
>> +                TCGv_i32 sr_ove = tcg_temp_local_new_i32();
>> +                if (rb == 0) {
>> +                    tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
>> +                    tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE);
>> +                    tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab0);
>> +                    gen_exception(dc, EXCP_RANGE);
>> +                    gen_set_label(lab0);
>> +                } else {
>> +                    tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[rb],
>> +                                       0x00000000, lab1);
>> +                    tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
>> +                    tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE);
>> +                    tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab1);
>
> Ditto.
>
>> +                    gen_exception(dc, EXCP_RANGE);
>> +                    gen_set_label(lab1);
>> +                    tcg_gen_divu_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
>> +                }
>> +                tcg_temp_free_i32(sr_ove);
>> +            }
>> +            break;
>
> [...]
>
>> +    case 0x000e:
>> +        switch (op1) {
>> +        case 0x00:   /*l.cmov*/
>> +            LOG_DIS("l.cmov r%d, r%d, r%d\n", rd, ra, rb);
>> +            {
>> +                int lab = gen_new_label();
>> +                TCGv res = tcg_temp_new();
>
> Need to be temp_local to survive brcond.
>

Thank you, fixed.

>> +                TCGv sr_f = tcg_temp_new();
>> +                tcg_gen_andi_tl(sr_f, cpu_sr, SR_F);
>> +                tcg_gen_mov_tl(res, cpu_R[rb]);
>> +                tcg_gen_brcondi_tl(TCG_COND_NE, sr_f, SR_F, lab);
>> +                tcg_gen_mov_tl(res, cpu_R[ra]);
>> +                gen_set_label(lab);
>> +                tcg_gen_mov_tl(cpu_R[rd], res);
>> +                tcg_temp_free(sr_f);
>> +                tcg_temp_free(res);
>> +            }
>> +            break;
>
> [...]
>
> --
> Thanks.
> -- Max

Regards,
Jia.