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[Qemu-devel] [PATCH v8 09/16] target-or32: Add PIC support
From: |
Jia Liu |
Subject: |
[Qemu-devel] [PATCH v8 09/16] target-or32: Add PIC support |
Date: |
Sun, 1 Jul 2012 10:45:23 +0800 |
Add OpenRISC Programmable Interrupt Controller support.
Signed-off-by: Jia Liu <address@hidden>
---
hw/openrisc/Makefile.objs | 2 ++
hw/openrisc_pic.c | 60 +++++++++++++++++++++++++++++++++++++++++++++
target-openrisc/cpu.h | 3 +++
3 files changed, 65 insertions(+)
create mode 100644 hw/openrisc_pic.c
diff --git a/hw/openrisc/Makefile.objs b/hw/openrisc/Makefile.objs
index bfead21..98900aa 100644
--- a/hw/openrisc/Makefile.objs
+++ b/hw/openrisc/Makefile.objs
@@ -1 +1,3 @@
+obj-y = openrisc_pic.o
+
obj-y := $(addprefix ../,$(obj-y))
diff --git a/hw/openrisc_pic.c b/hw/openrisc_pic.c
new file mode 100644
index 0000000..6b5b0f4
--- /dev/null
+++ b/hw/openrisc_pic.c
@@ -0,0 +1,60 @@
+/*
+ * OpenRISC Programmable Interrupt Controller support.
+ *
+ * Copyright (c) 2011-2012 Jia Liu <address@hidden>
+ * Feng Gao <address@hidden>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "hw.h"
+#include "cpu.h"
+
+/* OpenRISC pic handler */
+static void openrisc_pic_cpu_handler(void *opaque, int irq, int level)
+{
+ OpenRISCCPU *cpu = (OpenRISCCPU *)opaque;
+ int i;
+ uint32_t irq_bit = 1 << irq;
+
+ if (irq > 31 || irq < 0) {
+ return;
+ }
+
+ if (level) {
+ cpu->env.picsr |= irq_bit;
+ } else {
+ cpu->env.picsr &= ~irq_bit;
+ }
+
+ for (i = 0; i < 32; i++) {
+ if ((cpu->env.picsr && (1 << i)) && (cpu->env.picmr && (1 << i))) {
+ cpu_interrupt(&cpu->env, CPU_INTERRUPT_HARD);
+ } else {
+ cpu_reset_interrupt(&cpu->env, CPU_INTERRUPT_HARD);
+ cpu->env.picsr &= ~(1 << i);
+ }
+ }
+}
+
+void cpu_openrisc_pic_init(OpenRISCCPU *cpu)
+{
+ int i;
+ qemu_irq *qi;
+ qi = qemu_allocate_irqs(openrisc_pic_cpu_handler, cpu, NR_IRQS);
+
+ for (i = 0; i < NR_IRQS; i++) {
+ cpu->env.irq[i] = qi[i];
+ }
+}
diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
index f493bb2..81c7337 100644
--- a/target-openrisc/cpu.h
+++ b/target-openrisc/cpu.h
@@ -362,6 +362,9 @@ int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env,
#define CPU_SAVE_VERSION 1
#ifndef CONFIG_USER_ONLY
+/* hw/openrisc_pic.c */
+void cpu_openrisc_pic_init(OpenRISCCPU *cpu);
+
void cpu_openrisc_mmu_init(OpenRISCCPU *cpu);
int cpu_openrisc_get_phys_nommu(OpenRISCCPU *cpu,
target_phys_addr_t *physical,
--
1.7.9.5
- [Qemu-devel] [PATCH v8 00/16] QEMU OpenRISC support, Jia Liu, 2012/06/30
- [Qemu-devel] [PATCH v8 01/16] target-or32: Add target stubs and QOM cpu, Jia Liu, 2012/06/30
- [Qemu-devel] [PATCH v8 02/16] target-or32: Add target machine, Jia Liu, 2012/06/30
- [Qemu-devel] [PATCH v8 03/16] target-or32: Add MMU support, Jia Liu, 2012/06/30
- [Qemu-devel] [PATCH v8 04/16] target-or32: Add interrupt support, Jia Liu, 2012/06/30
- [Qemu-devel] [PATCH v8 05/16] target-or32: Add exception support, Jia Liu, 2012/06/30
- [Qemu-devel] [PATCH v8 06/16] target-or32: Add int instruction helpers, Jia Liu, 2012/06/30
- [Qemu-devel] [PATCH v8 08/16] target-or32: Add instruction translation, Jia Liu, 2012/06/30
- [Qemu-devel] [PATCH v8 09/16] target-or32: Add PIC support,
Jia Liu <=
- [Qemu-devel] [PATCH v8 11/16] target-or32: Add a IIS dummy board, Jia Liu, 2012/06/30
- [Qemu-devel] [PATCH v8 12/16] target-or32: Add system instructions, Jia Liu, 2012/06/30
- [Qemu-devel] [PATCH v8 13/16] target-or32: Add gdb stub support, Jia Liu, 2012/06/30
- [Qemu-devel] [PATCH v8 14/16] target-or32: Add linux syscall, signal and termbits, Jia Liu, 2012/06/30
- [Qemu-devel] [PATCH v8 15/16] target-or32: Add linux user support, Jia Liu, 2012/06/30
- [Qemu-devel] [PATCH v8 16/16] target-or32: Add testcases, Jia Liu, 2012/06/30
- [Qemu-devel] [PATCH v8 07/16] target-or32: Add float instruction helpers, Jia Liu, 2012/06/30
- [Qemu-devel] [PATCH v8 10/16] target-or32: Add timer support, Jia Liu, 2012/06/30