Re: [Qemu-devel] [PATCH V5 8/8] smb: replace_register_ioport*

[Jan Kiszka]

On 2012-08-22 14:27, Julien Grall wrote:
> This patch fix smb_ioport_* to be compliant with read/write memory callback.
> Moreover it replaces all register_ioport* which use theses functions by
> the new Memory API.
> 
> Signed-off-by: Julien Grall <address@hidden>
> ---
>  hw/pm_smbus.c |    7 ++++---
>  hw/pm_smbus.h |    6 ++++--
>  hw/vt82c686.c |   18 ++++++++++++++++--
>  3 files changed, 24 insertions(+), 7 deletions(-)
> 
> diff --git a/hw/pm_smbus.c b/hw/pm_smbus.c
> index 5d6046d..fe59ca6 100644
> --- a/hw/pm_smbus.c
> +++ b/hw/pm_smbus.c
> @@ -94,7 +94,8 @@ static void smb_transaction(PMSMBus *s)
>      s->smb_stat |= 0x04;
>  }
>  
> -void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
> +void smb_ioport_writeb(void *opaque, target_phys_addr_t addr, uint64_t val,
> +                       unsigned size)
>  {
>      PMSMBus *s = opaque;
>      addr &= 0x3f;
> @@ -131,10 +132,10 @@ void smb_ioport_writeb(void *opaque, uint32_t addr, 
> uint32_t val)
>      }
>  }
>  
> -uint32_t smb_ioport_readb(void *opaque, uint32_t addr)
> +uint64_t smb_ioport_readb(void *opaque, target_phys_addr_t addr, unsigned 
> size)
>  {
>      PMSMBus *s = opaque;
> -    uint32_t val;
> +    uint64_t val;
>  
>      addr &= 0x3f;
>      switch(addr) {
> diff --git a/hw/pm_smbus.h b/hw/pm_smbus.h
> index 4750a40..45b4330 100644
> --- a/hw/pm_smbus.h
> +++ b/hw/pm_smbus.h
> @@ -15,7 +15,9 @@ typedef struct PMSMBus {
>  } PMSMBus;
>  
>  void pm_smbus_init(DeviceState *parent, PMSMBus *smb);
> -void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val);
> -uint32_t smb_ioport_readb(void *opaque, uint32_t addr);
> +void smb_ioport_writeb(void *opaque, target_phys_addr_t addr, uint64_t val,
> +                       unsigned size);
> +uint64_t smb_ioport_readb(void *opaque, target_phys_addr_t addr,
> +                          unsigned size);
>  
>  #endif /* !PM_SMBUS_H */
> diff --git a/hw/vt82c686.c b/hw/vt82c686.c
> index 7f11dbe..6b35155 100644
> --- a/hw/vt82c686.c
> +++ b/hw/vt82c686.c
> @@ -163,6 +163,7 @@ typedef struct VT686PMState {
>      APMState apm;
>      PMSMBus smb;
>      uint32_t smb_io_base;
> +    MemoryRegion smb_io;
>  } VT686PMState;
>  
>  typedef struct VT686AC97State {
> @@ -405,6 +406,16 @@ static TypeInfo via_mc97_info = {
>      .class_init    = via_mc97_class_init,
>  };
>  
> +static const MemoryRegionOps smb_io_ops = {
> +    .read = smb_ioport_readb,
> +    .write = smb_ioport_writeb,
> +    .endianess = DEVICE_NATIVE_ENDIAN,
        ^^^^^^^^^
Typo. Please ensure that you build-test everything (full QEMU build).

> +    .impl = {
> +        .min_access_size = 1,
> +        .max_access_size = 1,
> +    },
> +};
> +
>  /* vt82c686 pm init */
>  static int vt82c686b_pm_initfn(PCIDevice *dev)
>  {
> @@ -424,8 +435,11 @@ static int vt82c686b_pm_initfn(PCIDevice *dev)
>      pci_conf[0x90] = s->smb_io_base | 1;
>      pci_conf[0x91] = s->smb_io_base >> 8;
>      pci_conf[0xd2] = 0x90;
> -    register_ioport_write(s->smb_io_base, 0xf, 1, smb_ioport_writeb, 
> &s->smb);
> -    register_ioport_read(s->smb_io_base, 0xf, 1, smb_ioport_readb, &s->smb);
> +
> +    memory_region_init_io(&s->smb_io, &smb_io_ops, &s->smb, "vt82c686b-smb",
> +                          0xf);
> +    memory_region_add_subregion(pci_address_space_io(dev), s->smb_io_base,
> +                                &s->smb_io);
>  
>      apm_init(dev, &s->apm, NULL, s);
>  
> 

This file is only half-converted. Working on the other bits...

Jan

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