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Re: [Qemu-devel] [PATCH 16/21] target-arm: switch to AREG0 free mode
|
From: |
Peter Maydell |
|
Subject: |
Re: [Qemu-devel] [PATCH 16/21] target-arm: switch to AREG0 free mode |
|
Date: |
Mon, 3 Sep 2012 01:01:03 +0100 |
On 2 September 2012 18:33, Blue Swirl <address@hidden> wrote:
> Add an explicit CPUState parameter instead of relying on AREG0
> and switch to AREG0 free mode.
>
> Signed-off-by: Blue Swirl <address@hidden>
> ---
> configure | 2 +-
> target-arm/Makefile.objs | 2 -
> target-arm/cpu.h | 10 ++-
> target-arm/helper.c | 8 +-
> target-arm/helper.h | 60 +++++++++---------
> target-arm/op_helper.c | 92 +++++++++++++---------------
> target-arm/translate.c | 148
> +++++++++++++++++++++++-----------------------
> 7 files changed, 158 insertions(+), 164 deletions(-)
This is too big to easily review -- it's making a change to a lot
of helpers, and in each case that change affects three places
(callers, declaration, implementation). That'
> diff --git a/configure b/configure
> index 4fd3b7f..efb5014 100755
> --- a/configure
> +++ b/configure
> @@ -3829,7 +3829,7 @@ symlink "$source_path/Makefile.target"
> "$target_dir/Makefile"
>
>
> case "$target_arch2" in
> - alpha | i386 | lm32 | m68k | or32 | s390x | sparc* | unicore32 | x86_64 |
> xtensa* | ppc*)
> + alpha | arm* | i386 | lm32 | m68k | or32 | s390x | sparc* | unicore32 |
> x86_64 | xtensa* | ppc*)
> echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
> ;;
> esac
> diff --git a/target-arm/Makefile.objs b/target-arm/Makefile.objs
> index f447c4f..b6f1a9e 100644
> --- a/target-arm/Makefile.objs
> +++ b/target-arm/Makefile.objs
> @@ -2,5 +2,3 @@ obj-y += arm-semi.o
> obj-$(CONFIG_SOFTMMU) += machine.o
> obj-y += translate.o op_helper.o helper.o cpu.o
> obj-y += neon_helper.o iwmmxt_helper.o
> -
> -$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index d7f93d9..7fac94f 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -734,9 +734,10 @@ static inline void cpu_pc_from_tb(CPUARMState *env,
> TranslationBlock *tb)
> }
>
> /* Load an instruction and return it in the standard little-endian order */
> -static inline uint32_t arm_ldl_code(uint32_t addr, bool do_swap)
> +static inline uint32_t arm_ldl_code(CPUARMState *env, uint32_t addr,
> + bool do_swap)
> {
> - uint32_t insn = ldl_code(addr);
> + uint32_t insn = cpu_ldl_code(env, addr);
> if (do_swap) {
> return bswap32(insn);
> }
> @@ -744,9 +745,10 @@ static inline uint32_t arm_ldl_code(uint32_t addr, bool
> do_swap)
> }
>
> /* Ditto, for a halfword (Thumb) instruction */
> -static inline uint16_t arm_lduw_code(uint32_t addr, bool do_swap)
> +static inline uint16_t arm_lduw_code(CPUARMState *env, uint32_t addr,
> + bool do_swap)
> {
> - uint16_t insn = lduw_code(addr);
> + uint16_t insn = cpu_lduw_code(env, addr);
> if (do_swap) {
> return bswap16(insn);
> }
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index dceaa95..f4d711c 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -1756,7 +1756,7 @@ static void do_interrupt_v7m(CPUARMState *env)
> case EXCP_BKPT:
> if (semihosting_enabled) {
> int nr;
> - nr = arm_lduw_code(env->regs[15], env->bswap_code) & 0xff;
> + nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
> if (nr == 0xab) {
> env->regs[15] += 2;
> env->regs[0] = do_arm_semihosting(env);
> @@ -1828,9 +1828,9 @@ void do_interrupt(CPUARMState *env)
> if (semihosting_enabled) {
> /* Check for semihosting interrupt. */
> if (env->thumb) {
> - mask = arm_lduw_code(env->regs[15] - 2, env->bswap_code) &
> 0xff;
> + mask = arm_lduw_code(env, env->regs[15] - 2,
> env->bswap_code) & 0xff;
> } else {
> - mask = arm_ldl_code(env->regs[15] - 4, env->bswap_code)
> + mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
> & 0xffffff;
> }
> /* Only intercept calls from privileged modes, to provide some
> @@ -1851,7 +1851,7 @@ void do_interrupt(CPUARMState *env)
> case EXCP_BKPT:
> /* See if this is a semihosting syscall. */
> if (env->thumb && semihosting_enabled) {
> - mask = arm_lduw_code(env->regs[15], env->bswap_code) & 0xff;
> + mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
> if (mask == 0xab
> && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
> env->regs[15] += 2;
> diff --git a/target-arm/helper.h b/target-arm/helper.h
> index 21e9cfe..afdb2b5 100644
> --- a/target-arm/helper.h
> +++ b/target-arm/helper.h
> @@ -4,12 +4,12 @@ DEF_HELPER_1(clz, i32, i32)
> DEF_HELPER_1(sxtb16, i32, i32)
> DEF_HELPER_1(uxtb16, i32, i32)
>
> -DEF_HELPER_2(add_setq, i32, i32, i32)
> -DEF_HELPER_2(add_saturate, i32, i32, i32)
> -DEF_HELPER_2(sub_saturate, i32, i32, i32)
> -DEF_HELPER_2(add_usaturate, i32, i32, i32)
> -DEF_HELPER_2(sub_usaturate, i32, i32, i32)
> -DEF_HELPER_1(double_saturate, i32, s32)
> +DEF_HELPER_3(add_setq, i32, env, i32, i32)
> +DEF_HELPER_3(add_saturate, i32, env, i32, i32)
> +DEF_HELPER_3(sub_saturate, i32, env, i32, i32)
> +DEF_HELPER_3(add_usaturate, i32, env, i32, i32)
> +DEF_HELPER_3(sub_usaturate, i32, env, i32, i32)
> +DEF_HELPER_2(double_saturate, i32, env, s32)
> DEF_HELPER_2(sdiv, s32, s32, s32)
> DEF_HELPER_2(udiv, i32, i32, i32)
> DEF_HELPER_1(rbit, i32, i32)
> @@ -40,21 +40,21 @@ PAS_OP(uq)
> PAS_OP(uh)
> #undef PAS_OP
>
> -DEF_HELPER_2(ssat, i32, i32, i32)
> -DEF_HELPER_2(usat, i32, i32, i32)
> -DEF_HELPER_2(ssat16, i32, i32, i32)
> -DEF_HELPER_2(usat16, i32, i32, i32)
> +DEF_HELPER_3(ssat, i32, env, i32, i32)
> +DEF_HELPER_3(usat, i32, env, i32, i32)
> +DEF_HELPER_3(ssat16, i32, env, i32, i32)
> +DEF_HELPER_3(usat16, i32, env, i32, i32)
>
> DEF_HELPER_2(usad8, i32, i32, i32)
>
> DEF_HELPER_1(logicq_cc, i32, i64)
>
> DEF_HELPER_3(sel_flags, i32, i32, i32, i32)
> -DEF_HELPER_1(exception, void, i32)
> -DEF_HELPER_0(wfi, void)
> +DEF_HELPER_2(exception, void, env, i32)
> +DEF_HELPER_1(wfi, void, env)
>
> -DEF_HELPER_2(cpsr_write, void, i32, i32)
> -DEF_HELPER_0(cpsr_read, i32)
> +DEF_HELPER_3(cpsr_write, void, env, i32, i32)
> +DEF_HELPER_1(cpsr_read, i32, env)
>
> DEF_HELPER_3(v7m_msr, void, env, i32, i32)
> DEF_HELPER_2(v7m_mrs, i32, env, i32)
> @@ -67,8 +67,8 @@ DEF_HELPER_2(get_cp_reg64, i64, env, ptr)
> DEF_HELPER_2(get_r13_banked, i32, env, i32)
> DEF_HELPER_3(set_r13_banked, void, env, i32, i32)
>
> -DEF_HELPER_1(get_user_reg, i32, i32)
> -DEF_HELPER_2(set_user_reg, void, i32, i32)
> +DEF_HELPER_2(get_user_reg, i32, env, i32)
> +DEF_HELPER_3(set_user_reg, void, env, i32, i32)
>
> DEF_HELPER_1(vfp_get_fpscr, i32, env)
> DEF_HELPER_2(vfp_set_fpscr, void, env, i32)
> @@ -140,20 +140,20 @@ DEF_HELPER_2(recpe_f32, f32, f32, env)
> DEF_HELPER_2(rsqrte_f32, f32, f32, env)
> DEF_HELPER_2(recpe_u32, i32, i32, env)
> DEF_HELPER_2(rsqrte_u32, i32, i32, env)
> -DEF_HELPER_4(neon_tbl, i32, i32, i32, i32, i32)
> -
> -DEF_HELPER_2(add_cc, i32, i32, i32)
> -DEF_HELPER_2(adc_cc, i32, i32, i32)
> -DEF_HELPER_2(sub_cc, i32, i32, i32)
> -DEF_HELPER_2(sbc_cc, i32, i32, i32)
> -
> -DEF_HELPER_2(shl, i32, i32, i32)
> -DEF_HELPER_2(shr, i32, i32, i32)
> -DEF_HELPER_2(sar, i32, i32, i32)
> -DEF_HELPER_2(shl_cc, i32, i32, i32)
> -DEF_HELPER_2(shr_cc, i32, i32, i32)
> -DEF_HELPER_2(sar_cc, i32, i32, i32)
> -DEF_HELPER_2(ror_cc, i32, i32, i32)
> +DEF_HELPER_5(neon_tbl, i32, env, i32, i32, i32, i32)
> +
> +DEF_HELPER_3(add_cc, i32, env, i32, i32)
> +DEF_HELPER_3(adc_cc, i32, env, i32, i32)
> +DEF_HELPER_3(sub_cc, i32, env, i32, i32)
> +DEF_HELPER_3(sbc_cc, i32, env, i32, i32)
> +
> +DEF_HELPER_3(shl, i32, env, i32, i32)
> +DEF_HELPER_3(shr, i32, env, i32, i32)
> +DEF_HELPER_3(sar, i32, env, i32, i32)
> +DEF_HELPER_3(shl_cc, i32, env, i32, i32)
> +DEF_HELPER_3(shr_cc, i32, env, i32, i32)
> +DEF_HELPER_3(sar_cc, i32, env, i32, i32)
> +DEF_HELPER_3(ror_cc, i32, env, i32, i32)
>
> /* neon_helper.c */
> DEF_HELPER_3(neon_qadd_u8, i32, env, i32, i32)
> diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
> index d77bfab..f13fc3a 100644
> --- a/target-arm/op_helper.c
> +++ b/target-arm/op_helper.c
> @@ -17,19 +17,18 @@
> * License along with this library; if not, see
> <http://www.gnu.org/licenses/>.
> */
> #include "cpu.h"
> -#include "dyngen-exec.h"
> #include "helper.h"
>
> #define SIGNBIT (uint32_t)0x80000000
> #define SIGNBIT64 ((uint64_t)1 << 63)
>
> -static void raise_exception(int tt)
> +static void raise_exception(CPUARMState *env, int tt)
> {
> env->exception_index = tt;
> cpu_loop_exit(env);
> }
>
> -uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def,
> +uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def,
> uint32_t rn, uint32_t maxindex)
> {
> uint32_t val;
> @@ -72,16 +71,12 @@ uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def,
> /* try to fill the TLB and return an exception if error. If retaddr is
> NULL, it means that the function was called in C code (i.e. not
> from generated code or from helper.c) */
> -/* XXX: fix it to restore all registers */
> -void tlb_fill(CPUARMState *env1, target_ulong addr, int is_write, int
> mmu_idx,
> +void tlb_fill(CPUARMState *env, target_ulong addr, int is_write, int mmu_idx,
> uintptr_t retaddr)
> {
> TranslationBlock *tb;
> - CPUARMState *saved_env;
> int ret;
>
> - saved_env = env;
> - env = env1;
> ret = cpu_arm_handle_mmu_fault(env, addr, is_write, mmu_idx);
> if (unlikely(ret)) {
> if (retaddr) {
> @@ -93,15 +88,14 @@ void tlb_fill(CPUARMState *env1, target_ulong addr, int
> is_write, int mmu_idx,
> cpu_restore_state(tb, env, retaddr);
> }
> }
> - raise_exception(env->exception_index);
> + raise_exception(env, env->exception_index);
> }
> - env = saved_env;
> }
> #endif
>
> /* FIXME: Pass an explicit pointer to QF to CPUARMState, and move saturating
> instructions into helper.c */
> -uint32_t HELPER(add_setq)(uint32_t a, uint32_t b)
> +uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b)
> {
> uint32_t res = a + b;
> if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT))
> @@ -109,7 +103,7 @@ uint32_t HELPER(add_setq)(uint32_t a, uint32_t b)
> return res;
> }
>
> -uint32_t HELPER(add_saturate)(uint32_t a, uint32_t b)
> +uint32_t HELPER(add_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
> {
> uint32_t res = a + b;
> if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT)) {
> @@ -119,7 +113,7 @@ uint32_t HELPER(add_saturate)(uint32_t a, uint32_t b)
> return res;
> }
>
> -uint32_t HELPER(sub_saturate)(uint32_t a, uint32_t b)
> +uint32_t HELPER(sub_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
> {
> uint32_t res = a - b;
> if (((res ^ a) & SIGNBIT) && ((a ^ b) & SIGNBIT)) {
> @@ -129,7 +123,7 @@ uint32_t HELPER(sub_saturate)(uint32_t a, uint32_t b)
> return res;
> }
>
> -uint32_t HELPER(double_saturate)(int32_t val)
> +uint32_t HELPER(double_saturate)(CPUARMState *env, int32_t val)
> {
> uint32_t res;
> if (val >= 0x40000000) {
> @@ -144,7 +138,7 @@ uint32_t HELPER(double_saturate)(int32_t val)
> return res;
> }
>
> -uint32_t HELPER(add_usaturate)(uint32_t a, uint32_t b)
> +uint32_t HELPER(add_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
> {
> uint32_t res = a + b;
> if (res < a) {
> @@ -154,7 +148,7 @@ uint32_t HELPER(add_usaturate)(uint32_t a, uint32_t b)
> return res;
> }
>
> -uint32_t HELPER(sub_usaturate)(uint32_t a, uint32_t b)
> +uint32_t HELPER(sub_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
> {
> uint32_t res = a - b;
> if (res > a) {
> @@ -165,7 +159,7 @@ uint32_t HELPER(sub_usaturate)(uint32_t a, uint32_t b)
> }
>
> /* Signed saturation. */
> -static inline uint32_t do_ssat(int32_t val, int shift)
> +static inline uint32_t do_ssat(CPUARMState *env, int32_t val, int shift)
> {
> int32_t top;
> uint32_t mask;
> @@ -183,7 +177,7 @@ static inline uint32_t do_ssat(int32_t val, int shift)
> }
>
> /* Unsigned saturation. */
> -static inline uint32_t do_usat(int32_t val, int shift)
> +static inline uint32_t do_usat(CPUARMState *env, int32_t val, int shift)
> {
> uint32_t max;
>
> @@ -199,62 +193,62 @@ static inline uint32_t do_usat(int32_t val, int shift)
> }
>
> /* Signed saturate. */
> -uint32_t HELPER(ssat)(uint32_t x, uint32_t shift)
> +uint32_t HELPER(ssat)(CPUARMState *env, uint32_t x, uint32_t shift)
> {
> - return do_ssat(x, shift);
> + return do_ssat(env, x, shift);
> }
>
> /* Dual halfword signed saturate. */
> -uint32_t HELPER(ssat16)(uint32_t x, uint32_t shift)
> +uint32_t HELPER(ssat16)(CPUARMState *env, uint32_t x, uint32_t shift)
> {
> uint32_t res;
>
> - res = (uint16_t)do_ssat((int16_t)x, shift);
> - res |= do_ssat(((int32_t)x) >> 16, shift) << 16;
> + res = (uint16_t)do_ssat(env, (int16_t)x, shift);
> + res |= do_ssat(env, ((int32_t)x) >> 16, shift) << 16;
> return res;
> }
>
> /* Unsigned saturate. */
> -uint32_t HELPER(usat)(uint32_t x, uint32_t shift)
> +uint32_t HELPER(usat)(CPUARMState *env, uint32_t x, uint32_t shift)
> {
> - return do_usat(x, shift);
> + return do_usat(env, x, shift);
> }
>
> /* Dual halfword unsigned saturate. */
> -uint32_t HELPER(usat16)(uint32_t x, uint32_t shift)
> +uint32_t HELPER(usat16)(CPUARMState *env, uint32_t x, uint32_t shift)
> {
> uint32_t res;
>
> - res = (uint16_t)do_usat((int16_t)x, shift);
> - res |= do_usat(((int32_t)x) >> 16, shift) << 16;
> + res = (uint16_t)do_usat(env, (int16_t)x, shift);
> + res |= do_usat(env, ((int32_t)x) >> 16, shift) << 16;
> return res;
> }
>
> -void HELPER(wfi)(void)
> +void HELPER(wfi)(CPUARMState *env)
> {
> env->exception_index = EXCP_HLT;
> env->halted = 1;
> cpu_loop_exit(env);
> }
>
> -void HELPER(exception)(uint32_t excp)
> +void HELPER(exception)(CPUARMState *env, uint32_t excp)
> {
> env->exception_index = excp;
> cpu_loop_exit(env);
> }
>
> -uint32_t HELPER(cpsr_read)(void)
> +uint32_t HELPER(cpsr_read)(CPUARMState *env)
> {
> return cpsr_read(env) & ~CPSR_EXEC;
> }
>
> -void HELPER(cpsr_write)(uint32_t val, uint32_t mask)
> +void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask)
> {
> cpsr_write(env, val, mask);
> }
>
> /* Access to user mode registers from privileged modes. */
> -uint32_t HELPER(get_user_reg)(uint32_t regno)
> +uint32_t HELPER(get_user_reg)(CPUARMState *env, uint32_t regno)
> {
> uint32_t val;
>
> @@ -271,7 +265,7 @@ uint32_t HELPER(get_user_reg)(uint32_t regno)
> return val;
> }
>
> -void HELPER(set_user_reg)(uint32_t regno, uint32_t val)
> +void HELPER(set_user_reg)(CPUARMState *env, uint32_t regno, uint32_t val)
> {
> if (regno == 13) {
> env->banked_r13[0] = val;
> @@ -290,7 +284,7 @@ void HELPER(set_cp_reg)(CPUARMState *env, void *rip,
> uint32_t value)
> const ARMCPRegInfo *ri = rip;
> int excp = ri->writefn(env, ri, value);
> if (excp) {
> - raise_exception(excp);
> + raise_exception(env, excp);
> }
> }
>
> @@ -300,7 +294,7 @@ uint32_t HELPER(get_cp_reg)(CPUARMState *env, void *rip)
> uint64_t value;
> int excp = ri->readfn(env, ri, &value);
> if (excp) {
> - raise_exception(excp);
> + raise_exception(env, excp);
> }
> return value;
> }
> @@ -310,7 +304,7 @@ void HELPER(set_cp_reg64)(CPUARMState *env, void *rip,
> uint64_t value)
> const ARMCPRegInfo *ri = rip;
> int excp = ri->writefn(env, ri, value);
> if (excp) {
> - raise_exception(excp);
> + raise_exception(env, excp);
> }
> }
>
> @@ -320,7 +314,7 @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip)
> uint64_t value;
> int excp = ri->readfn(env, ri, &value);
> if (excp) {
> - raise_exception(excp);
> + raise_exception(env, excp);
> }
> return value;
> }
> @@ -329,7 +323,7 @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip)
> The only way to do that in TCG is a conditional branch, which clobbers
> all our temporaries. For now implement these as helper functions. */
>
> -uint32_t HELPER (add_cc)(uint32_t a, uint32_t b)
> +uint32_t HELPER (add_cc)(CPUARMState *env, uint32_t a, uint32_t b)
> {
> uint32_t result;
> result = a + b;
> @@ -339,7 +333,7 @@ uint32_t HELPER (add_cc)(uint32_t a, uint32_t b)
> return result;
> }
>
> -uint32_t HELPER(adc_cc)(uint32_t a, uint32_t b)
> +uint32_t HELPER(adc_cc)(CPUARMState *env, uint32_t a, uint32_t b)
> {
> uint32_t result;
> if (!env->CF) {
> @@ -354,7 +348,7 @@ uint32_t HELPER(adc_cc)(uint32_t a, uint32_t b)
> return result;
> }
>
> -uint32_t HELPER(sub_cc)(uint32_t a, uint32_t b)
> +uint32_t HELPER(sub_cc)(CPUARMState *env, uint32_t a, uint32_t b)
> {
> uint32_t result;
> result = a - b;
> @@ -364,7 +358,7 @@ uint32_t HELPER(sub_cc)(uint32_t a, uint32_t b)
> return result;
> }
>
> -uint32_t HELPER(sbc_cc)(uint32_t a, uint32_t b)
> +uint32_t HELPER(sbc_cc)(CPUARMState *env, uint32_t a, uint32_t b)
> {
> uint32_t result;
> if (!env->CF) {
> @@ -381,7 +375,7 @@ uint32_t HELPER(sbc_cc)(uint32_t a, uint32_t b)
>
> /* Similarly for variable shift instructions. */
>
> -uint32_t HELPER(shl)(uint32_t x, uint32_t i)
> +uint32_t HELPER(shl)(CPUARMState *env, uint32_t x, uint32_t i)
> {
> int shift = i & 0xff;
> if (shift >= 32)
> @@ -389,7 +383,7 @@ uint32_t HELPER(shl)(uint32_t x, uint32_t i)
> return x << shift;
> }
>
> -uint32_t HELPER(shr)(uint32_t x, uint32_t i)
> +uint32_t HELPER(shr)(CPUARMState *env, uint32_t x, uint32_t i)
> {
> int shift = i & 0xff;
> if (shift >= 32)
> @@ -397,7 +391,7 @@ uint32_t HELPER(shr)(uint32_t x, uint32_t i)
> return (uint32_t)x >> shift;
> }
>
> -uint32_t HELPER(sar)(uint32_t x, uint32_t i)
> +uint32_t HELPER(sar)(CPUARMState *env, uint32_t x, uint32_t i)
> {
> int shift = i & 0xff;
> if (shift >= 32)
> @@ -405,7 +399,7 @@ uint32_t HELPER(sar)(uint32_t x, uint32_t i)
> return (int32_t)x >> shift;
> }
>
> -uint32_t HELPER(shl_cc)(uint32_t x, uint32_t i)
> +uint32_t HELPER(shl_cc)(CPUARMState *env, uint32_t x, uint32_t i)
> {
> int shift = i & 0xff;
> if (shift >= 32) {
> @@ -421,7 +415,7 @@ uint32_t HELPER(shl_cc)(uint32_t x, uint32_t i)
> return x;
> }
>
> -uint32_t HELPER(shr_cc)(uint32_t x, uint32_t i)
> +uint32_t HELPER(shr_cc)(CPUARMState *env, uint32_t x, uint32_t i)
> {
> int shift = i & 0xff;
> if (shift >= 32) {
> @@ -437,7 +431,7 @@ uint32_t HELPER(shr_cc)(uint32_t x, uint32_t i)
> return x;
> }
>
> -uint32_t HELPER(sar_cc)(uint32_t x, uint32_t i)
> +uint32_t HELPER(sar_cc)(CPUARMState *env, uint32_t x, uint32_t i)
> {
> int shift = i & 0xff;
> if (shift >= 32) {
> @@ -450,7 +444,7 @@ uint32_t HELPER(sar_cc)(uint32_t x, uint32_t i)
> return x;
> }
>
> -uint32_t HELPER(ror_cc)(uint32_t x, uint32_t i)
> +uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i)
> {
> int shift1, shift;
> shift1 = i & 0xff;
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index edef79a..f4b447a 100644
> --- a/target-arm/translate.c
> +++ b/target-arm/translate.c
> @@ -199,7 +199,7 @@ static void store_reg(DisasContext *s, int reg, TCGv var)
> static inline void gen_set_cpsr(TCGv var, uint32_t mask)
> {
> TCGv tmp_mask = tcg_const_i32(mask);
> - gen_helper_cpsr_write(var, tmp_mask);
> + gen_helper_cpsr_write(cpu_env, var, tmp_mask);
> tcg_temp_free_i32(tmp_mask);
> }
> /* Set NZCV flags from the high 4 bits of var. */
> @@ -209,7 +209,7 @@ static void gen_exception(int excp)
> {
> TCGv tmp = tcg_temp_new_i32();
> tcg_gen_movi_i32(tmp, excp);
> - gen_helper_exception(tmp);
> + gen_helper_exception(cpu_env, tmp);
> tcg_temp_free_i32(tmp);
> }
>
> @@ -490,16 +490,16 @@ static inline void gen_arm_shift_reg(TCGv var, int
> shiftop,
> {
> if (flags) {
> switch (shiftop) {
> - case 0: gen_helper_shl_cc(var, var, shift); break;
> - case 1: gen_helper_shr_cc(var, var, shift); break;
> - case 2: gen_helper_sar_cc(var, var, shift); break;
> - case 3: gen_helper_ror_cc(var, var, shift); break;
> + case 0: gen_helper_shl_cc(var, cpu_env, var, shift); break;
> + case 1: gen_helper_shr_cc(var, cpu_env, var, shift); break;
> + case 2: gen_helper_sar_cc(var, cpu_env, var, shift); break;
> + case 3: gen_helper_ror_cc(var, cpu_env, var, shift); break;
> }
> } else {
> switch (shiftop) {
> - case 0: gen_helper_shl(var, var, shift); break;
> - case 1: gen_helper_shr(var, var, shift); break;
> - case 2: gen_helper_sar(var, var, shift); break;
> + case 0: gen_helper_shl(var, cpu_env, var, shift); break;
> + case 1: gen_helper_shr(var, cpu_env, var, shift); break;
> + case 2: gen_helper_sar(var, cpu_env, var, shift); break;
> case 3: tcg_gen_andi_i32(shift, shift, 0x1f);
> tcg_gen_rotr_i32(var, var, shift); break;
> }
> @@ -6121,7 +6121,7 @@ static int disas_neon_data_insn(CPUARMState * env,
> DisasContext *s, uint32_t ins
> tmp2 = neon_load_reg(rm, 0);
> tmp4 = tcg_const_i32(rn);
> tmp5 = tcg_const_i32(n);
> - gen_helper_neon_tbl(tmp2, tmp2, tmp, tmp4, tmp5);
> + gen_helper_neon_tbl(tmp2, cpu_env, tmp2, tmp, tmp4, tmp5);
> tcg_temp_free_i32(tmp);
> if (insn & (1 << 6)) {
> tmp = neon_load_reg(rd, 1);
> @@ -6130,7 +6130,7 @@ static int disas_neon_data_insn(CPUARMState * env,
> DisasContext *s, uint32_t ins
> tcg_gen_movi_i32(tmp, 0);
> }
> tmp3 = neon_load_reg(rm, 1);
> - gen_helper_neon_tbl(tmp3, tmp3, tmp, tmp4, tmp5);
> + gen_helper_neon_tbl(tmp3, cpu_env, tmp3, tmp, tmp4, tmp5);
> tcg_temp_free_i32(tmp5);
> tcg_temp_free_i32(tmp4);
> neon_store_reg(rd, 0, tmp2);
> @@ -6534,7 +6534,7 @@ static void disas_arm_insn(CPUARMState * env,
> DisasContext *s)
> TCGv addr;
> TCGv_i64 tmp64;
>
> - insn = arm_ldl_code(s->pc, s->bswap_code);
> + insn = arm_ldl_code(env, s->pc, s->bswap_code);
> s->pc += 4;
>
> /* M variants do not implement ARM mode. */
> @@ -6818,7 +6818,7 @@ static void disas_arm_insn(CPUARMState * env,
> DisasContext *s)
> tmp = load_cpu_field(spsr);
> } else {
> tmp = tcg_temp_new_i32();
> - gen_helper_cpsr_read(tmp);
> + gen_helper_cpsr_read(tmp, cpu_env);
> }
> store_reg(s, rd, tmp);
> }
> @@ -6869,11 +6869,11 @@ static void disas_arm_insn(CPUARMState * env,
> DisasContext *s)
> tmp = load_reg(s, rm);
> tmp2 = load_reg(s, rn);
> if (op1 & 2)
> - gen_helper_double_saturate(tmp2, tmp2);
> + gen_helper_double_saturate(tmp2, cpu_env, tmp2);
> if (op1 & 1)
> - gen_helper_sub_saturate(tmp, tmp, tmp2);
> + gen_helper_sub_saturate(tmp, cpu_env, tmp, tmp2);
> else
> - gen_helper_add_saturate(tmp, tmp, tmp2);
> + gen_helper_add_saturate(tmp, cpu_env, tmp, tmp2);
> tcg_temp_free_i32(tmp2);
> store_reg(s, rd, tmp);
> break;
> @@ -6911,7 +6911,7 @@ static void disas_arm_insn(CPUARMState * env,
> DisasContext *s)
> tcg_temp_free_i64(tmp64);
> if ((sh & 2) == 0) {
> tmp2 = load_reg(s, rn);
> - gen_helper_add_setq(tmp, tmp, tmp2);
> + gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
> tcg_temp_free_i32(tmp2);
> }
> store_reg(s, rd, tmp);
> @@ -6931,7 +6931,7 @@ static void disas_arm_insn(CPUARMState * env,
> DisasContext *s)
> } else {
> if (op1 == 0) {
> tmp2 = load_reg(s, rn);
> - gen_helper_add_setq(tmp, tmp, tmp2);
> + gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
> tcg_temp_free_i32(tmp2);
> }
> store_reg(s, rd, tmp);
> @@ -7005,11 +7005,11 @@ static void disas_arm_insn(CPUARMState * env,
> DisasContext *s)
> if (IS_USER(s)) {
> goto illegal_op;
> }
> - gen_helper_sub_cc(tmp, tmp, tmp2);
> + gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
> gen_exception_return(s, tmp);
> } else {
> if (set_cc) {
> - gen_helper_sub_cc(tmp, tmp, tmp2);
> + gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
> } else {
> tcg_gen_sub_i32(tmp, tmp, tmp2);
> }
> @@ -7018,7 +7018,7 @@ static void disas_arm_insn(CPUARMState * env,
> DisasContext *s)
> break;
> case 0x03:
> if (set_cc) {
> - gen_helper_sub_cc(tmp, tmp2, tmp);
> + gen_helper_sub_cc(tmp, cpu_env, tmp2, tmp);
> } else {
> tcg_gen_sub_i32(tmp, tmp2, tmp);
> }
> @@ -7026,7 +7026,7 @@ static void disas_arm_insn(CPUARMState * env,
> DisasContext *s)
> break;
> case 0x04:
> if (set_cc) {
> - gen_helper_add_cc(tmp, tmp, tmp2);
> + gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
> } else {
> tcg_gen_add_i32(tmp, tmp, tmp2);
> }
> @@ -7034,7 +7034,7 @@ static void disas_arm_insn(CPUARMState * env,
> DisasContext *s)
> break;
> case 0x05:
> if (set_cc) {
> - gen_helper_adc_cc(tmp, tmp, tmp2);
> + gen_helper_adc_cc(tmp, cpu_env, tmp, tmp2);
> } else {
> gen_add_carry(tmp, tmp, tmp2);
> }
> @@ -7042,7 +7042,7 @@ static void disas_arm_insn(CPUARMState * env,
> DisasContext *s)
> break;
> case 0x06:
> if (set_cc) {
> - gen_helper_sbc_cc(tmp, tmp, tmp2);
> + gen_helper_sbc_cc(tmp, cpu_env, tmp, tmp2);
> } else {
> gen_sub_carry(tmp, tmp, tmp2);
> }
> @@ -7050,7 +7050,7 @@ static void disas_arm_insn(CPUARMState * env,
> DisasContext *s)
> break;
> case 0x07:
> if (set_cc) {
> - gen_helper_sbc_cc(tmp, tmp2, tmp);
> + gen_helper_sbc_cc(tmp, cpu_env, tmp2, tmp);
> } else {
> gen_sub_carry(tmp, tmp2, tmp);
> }
> @@ -7072,13 +7072,13 @@ static void disas_arm_insn(CPUARMState * env,
> DisasContext *s)
> break;
> case 0x0a:
> if (set_cc) {
> - gen_helper_sub_cc(tmp, tmp, tmp2);
> + gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
> }
> tcg_temp_free_i32(tmp);
> break;
> case 0x0b:
> if (set_cc) {
> - gen_helper_add_cc(tmp, tmp, tmp2);
> + gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
> }
> tcg_temp_free_i32(tmp);
> break;
> @@ -7395,9 +7395,9 @@ static void disas_arm_insn(CPUARMState * env,
> DisasContext *s)
> sh = (insn >> 16) & 0x1f;
> tmp2 = tcg_const_i32(sh);
> if (insn & (1 << 22))
> - gen_helper_usat(tmp, tmp, tmp2);
> + gen_helper_usat(tmp, cpu_env, tmp, tmp2);
> else
> - gen_helper_ssat(tmp, tmp, tmp2);
> + gen_helper_ssat(tmp, cpu_env, tmp, tmp2);
> tcg_temp_free_i32(tmp2);
> store_reg(s, rd, tmp);
> } else if ((insn & 0x00300fe0) == 0x00200f20) {
> @@ -7406,9 +7406,9 @@ static void disas_arm_insn(CPUARMState * env,
> DisasContext *s)
> sh = (insn >> 16) & 0x1f;
> tmp2 = tcg_const_i32(sh);
> if (insn & (1 << 22))
> - gen_helper_usat16(tmp, tmp, tmp2);
> + gen_helper_usat16(tmp, cpu_env, tmp, tmp2);
> else
> - gen_helper_ssat16(tmp, tmp, tmp2);
> + gen_helper_ssat16(tmp, cpu_env, tmp, tmp2);
> tcg_temp_free_i32(tmp2);
> store_reg(s, rd, tmp);
> } else if ((insn & 0x00700fe0) == 0x00000fa0) {
> @@ -7518,7 +7518,7 @@ static void disas_arm_insn(CPUARMState * env,
> DisasContext *s)
> * however it may overflow considered as a signed
> * operation, in which case we must set the Q
> flag.
> */
> - gen_helper_add_setq(tmp, tmp, tmp2);
> + gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
> }
> tcg_temp_free_i32(tmp2);
> if (insn & (1 << 22)) {
> @@ -7534,7 +7534,7 @@ static void disas_arm_insn(CPUARMState * env,
> DisasContext *s)
> if (rd != 15)
> {
> tmp2 = load_reg(s, rd);
> - gen_helper_add_setq(tmp, tmp, tmp2);
> + gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
> tcg_temp_free_i32(tmp2);
> }
> store_reg(s, rn, tmp);
> @@ -7719,7 +7719,7 @@ static void disas_arm_insn(CPUARMState * env,
> DisasContext *s)
> tmp = gen_ld32(addr, IS_USER(s));
> if (user) {
> tmp2 = tcg_const_i32(i);
> - gen_helper_set_user_reg(tmp2, tmp);
> + gen_helper_set_user_reg(cpu_env, tmp2, tmp);
> tcg_temp_free_i32(tmp2);
> tcg_temp_free_i32(tmp);
> } else if (i == rn) {
> @@ -7738,7 +7738,7 @@ static void disas_arm_insn(CPUARMState * env,
> DisasContext *s)
> } else if (user) {
> tmp = tcg_temp_new_i32();
> tmp2 = tcg_const_i32(i);
> - gen_helper_get_user_reg(tmp, tmp2);
> + gen_helper_get_user_reg(tmp, cpu_env, tmp2);
> tcg_temp_free_i32(tmp2);
> } else {
> tmp = load_reg(s, i);
> @@ -7865,31 +7865,31 @@ gen_thumb2_data_op(DisasContext *s, int op, int
> conds, uint32_t shifter_out, TCG
> break;
> case 8: /* add */
> if (conds)
> - gen_helper_add_cc(t0, t0, t1);
> + gen_helper_add_cc(t0, cpu_env, t0, t1);
> else
> tcg_gen_add_i32(t0, t0, t1);
> break;
> case 10: /* adc */
> if (conds)
> - gen_helper_adc_cc(t0, t0, t1);
> + gen_helper_adc_cc(t0, cpu_env, t0, t1);
> else
> gen_adc(t0, t1);
> break;
> case 11: /* sbc */
> if (conds)
> - gen_helper_sbc_cc(t0, t0, t1);
> + gen_helper_sbc_cc(t0, cpu_env, t0, t1);
> else
> gen_sub_carry(t0, t0, t1);
> break;
> case 13: /* sub */
> if (conds)
> - gen_helper_sub_cc(t0, t0, t1);
> + gen_helper_sub_cc(t0, cpu_env, t0, t1);
> else
> tcg_gen_sub_i32(t0, t0, t1);
> break;
> case 14: /* rsb */
> if (conds)
> - gen_helper_sub_cc(t0, t1, t0);
> + gen_helper_sub_cc(t0, cpu_env, t1, t0);
> else
> tcg_gen_sub_i32(t0, t1, t0);
> break;
> @@ -7962,7 +7962,7 @@ static int disas_thumb2_insn(CPUARMState *env,
> DisasContext *s, uint16_t insn_hw
> /* Fall through to 32-bit decode. */
> }
>
> - insn = arm_lduw_code(s->pc, s->bswap_code);
> + insn = arm_lduw_code(env, s->pc, s->bswap_code);
> s->pc += 2;
> insn |= (uint32_t)insn_hw1 << 16;
>
> @@ -8111,7 +8111,7 @@ static int disas_thumb2_insn(CPUARMState *env,
> DisasContext *s, uint16_t insn_hw
> gen_st32(tmp, addr, 0);
> tcg_gen_addi_i32(addr, addr, 4);
> tmp = tcg_temp_new_i32();
> - gen_helper_cpsr_read(tmp);
> + gen_helper_cpsr_read(tmp, cpu_env);
> gen_st32(tmp, addr, 0);
> if (insn & (1 << 21)) {
> if ((insn & (1 << 24)) == 0) {
> @@ -8293,11 +8293,11 @@ static int disas_thumb2_insn(CPUARMState *env,
> DisasContext *s, uint16_t insn_hw
> tmp = load_reg(s, rn);
> tmp2 = load_reg(s, rm);
> if (op & 1)
> - gen_helper_double_saturate(tmp, tmp);
> + gen_helper_double_saturate(tmp, cpu_env, tmp);
> if (op & 2)
> - gen_helper_sub_saturate(tmp, tmp2, tmp);
> + gen_helper_sub_saturate(tmp, cpu_env, tmp2, tmp);
> else
> - gen_helper_add_saturate(tmp, tmp, tmp2);
> + gen_helper_add_saturate(tmp, cpu_env, tmp, tmp2);
> tcg_temp_free_i32(tmp2);
> } else {
> tmp = load_reg(s, rn);
> @@ -8353,7 +8353,7 @@ static int disas_thumb2_insn(CPUARMState *env,
> DisasContext *s, uint16_t insn_hw
> tcg_temp_free_i32(tmp2);
> if (rs != 15) {
> tmp2 = load_reg(s, rs);
> - gen_helper_add_setq(tmp, tmp, tmp2);
> + gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
> tcg_temp_free_i32(tmp2);
> }
> break;
> @@ -8370,13 +8370,13 @@ static int disas_thumb2_insn(CPUARMState *env,
> DisasContext *s, uint16_t insn_hw
> * however it may overflow considered as a signed
> * operation, in which case we must set the Q flag.
> */
> - gen_helper_add_setq(tmp, tmp, tmp2);
> + gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
> }
> tcg_temp_free_i32(tmp2);
> if (rs != 15)
> {
> tmp2 = load_reg(s, rs);
> - gen_helper_add_setq(tmp, tmp, tmp2);
> + gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
> tcg_temp_free_i32(tmp2);
> }
> break;
> @@ -8393,7 +8393,7 @@ static int disas_thumb2_insn(CPUARMState *env,
> DisasContext *s, uint16_t insn_hw
> if (rs != 15)
> {
> tmp2 = load_reg(s, rs);
> - gen_helper_add_setq(tmp, tmp, tmp2);
> + gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
> tcg_temp_free_i32(tmp2);
> }
> break;
> @@ -8632,7 +8632,7 @@ static int disas_thumb2_insn(CPUARMState *env,
> DisasContext *s, uint16_t insn_hw
> gen_helper_v7m_mrs(tmp, cpu_env, addr);
> tcg_temp_free_i32(addr);
> } else {
> - gen_helper_cpsr_read(tmp);
> + gen_helper_cpsr_read(tmp, cpu_env);
> }
> store_reg(s, rd, tmp);
> break;
> @@ -8721,15 +8721,15 @@ static int disas_thumb2_insn(CPUARMState *env,
> DisasContext *s, uint16_t insn_hw
> if (op & 4) {
> /* Unsigned. */
> if ((op & 1) && shift == 0)
> - gen_helper_usat16(tmp, tmp, tmp2);
> + gen_helper_usat16(tmp, cpu_env, tmp, tmp2);
> else
> - gen_helper_usat(tmp, tmp, tmp2);
> + gen_helper_usat(tmp, cpu_env, tmp, tmp2);
> } else {
> /* Signed. */
> if ((op & 1) && shift == 0)
> - gen_helper_ssat16(tmp, tmp, tmp2);
> + gen_helper_ssat16(tmp, cpu_env, tmp, tmp2);
> else
> - gen_helper_ssat(tmp, tmp, tmp2);
> + gen_helper_ssat(tmp, cpu_env, tmp, tmp2);
> }
> tcg_temp_free_i32(tmp2);
> break;
> @@ -8992,7 +8992,7 @@ static void disas_thumb_insn(CPUARMState *env,
> DisasContext *s)
> }
> }
>
> - insn = arm_lduw_code(s->pc, s->bswap_code);
> + insn = arm_lduw_code(env, s->pc, s->bswap_code);
> s->pc += 2;
>
> switch (insn >> 12) {
> @@ -9017,12 +9017,12 @@ static void disas_thumb_insn(CPUARMState *env,
> DisasContext *s)
> if (s->condexec_mask)
> tcg_gen_sub_i32(tmp, tmp, tmp2);
> else
> - gen_helper_sub_cc(tmp, tmp, tmp2);
> + gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
> } else {
> if (s->condexec_mask)
> tcg_gen_add_i32(tmp, tmp, tmp2);
> else
> - gen_helper_add_cc(tmp, tmp, tmp2);
> + gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
> }
> tcg_temp_free_i32(tmp2);
> store_reg(s, rd, tmp);
> @@ -9053,7 +9053,7 @@ static void disas_thumb_insn(CPUARMState *env,
> DisasContext *s)
> tcg_gen_movi_i32(tmp2, insn & 0xff);
> switch (op) {
> case 1: /* cmp */
> - gen_helper_sub_cc(tmp, tmp, tmp2);
> + gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
> tcg_temp_free_i32(tmp);
> tcg_temp_free_i32(tmp2);
> break;
> @@ -9061,7 +9061,7 @@ static void disas_thumb_insn(CPUARMState *env,
> DisasContext *s)
> if (s->condexec_mask)
> tcg_gen_add_i32(tmp, tmp, tmp2);
> else
> - gen_helper_add_cc(tmp, tmp, tmp2);
> + gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
> tcg_temp_free_i32(tmp2);
> store_reg(s, rd, tmp);
> break;
> @@ -9069,7 +9069,7 @@ static void disas_thumb_insn(CPUARMState *env,
> DisasContext *s)
> if (s->condexec_mask)
> tcg_gen_sub_i32(tmp, tmp, tmp2);
> else
> - gen_helper_sub_cc(tmp, tmp, tmp2);
> + gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
> tcg_temp_free_i32(tmp2);
> store_reg(s, rd, tmp);
> break;
> @@ -9105,7 +9105,7 @@ static void disas_thumb_insn(CPUARMState *env,
> DisasContext *s)
> case 1: /* cmp */
> tmp = load_reg(s, rd);
> tmp2 = load_reg(s, rm);
> - gen_helper_sub_cc(tmp, tmp, tmp2);
> + gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
> tcg_temp_free_i32(tmp2);
> tcg_temp_free_i32(tmp);
> break;
> @@ -9166,25 +9166,25 @@ static void disas_thumb_insn(CPUARMState *env,
> DisasContext *s)
> break;
> case 0x2: /* lsl */
> if (s->condexec_mask) {
> - gen_helper_shl(tmp2, tmp2, tmp);
> + gen_helper_shl(tmp2, cpu_env, tmp2, tmp);
> } else {
> - gen_helper_shl_cc(tmp2, tmp2, tmp);
> + gen_helper_shl_cc(tmp2, cpu_env, tmp2, tmp);
> gen_logic_CC(tmp2);
> }
> break;
> case 0x3: /* lsr */
> if (s->condexec_mask) {
> - gen_helper_shr(tmp2, tmp2, tmp);
> + gen_helper_shr(tmp2, cpu_env, tmp2, tmp);
> } else {
> - gen_helper_shr_cc(tmp2, tmp2, tmp);
> + gen_helper_shr_cc(tmp2, cpu_env, tmp2, tmp);
> gen_logic_CC(tmp2);
> }
> break;
> case 0x4: /* asr */
> if (s->condexec_mask) {
> - gen_helper_sar(tmp2, tmp2, tmp);
> + gen_helper_sar(tmp2, cpu_env, tmp2, tmp);
> } else {
> - gen_helper_sar_cc(tmp2, tmp2, tmp);
> + gen_helper_sar_cc(tmp2, cpu_env, tmp2, tmp);
> gen_logic_CC(tmp2);
> }
> break;
> @@ -9192,20 +9192,20 @@ static void disas_thumb_insn(CPUARMState *env,
> DisasContext *s)
> if (s->condexec_mask)
> gen_adc(tmp, tmp2);
> else
> - gen_helper_adc_cc(tmp, tmp, tmp2);
> + gen_helper_adc_cc(tmp, cpu_env, tmp, tmp2);
> break;
> case 0x6: /* sbc */
> if (s->condexec_mask)
> gen_sub_carry(tmp, tmp, tmp2);
> else
> - gen_helper_sbc_cc(tmp, tmp, tmp2);
> + gen_helper_sbc_cc(tmp, cpu_env, tmp, tmp2);
> break;
> case 0x7: /* ror */
> if (s->condexec_mask) {
> tcg_gen_andi_i32(tmp, tmp, 0x1f);
> tcg_gen_rotr_i32(tmp2, tmp2, tmp);
> } else {
> - gen_helper_ror_cc(tmp2, tmp2, tmp);
> + gen_helper_ror_cc(tmp2, cpu_env, tmp2, tmp);
> gen_logic_CC(tmp2);
> }
> break;
> @@ -9218,14 +9218,14 @@ static void disas_thumb_insn(CPUARMState *env,
> DisasContext *s)
> if (s->condexec_mask)
> tcg_gen_neg_i32(tmp, tmp2);
> else
> - gen_helper_sub_cc(tmp, tmp, tmp2);
> + gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
> break;
> case 0xa: /* cmp */
> - gen_helper_sub_cc(tmp, tmp, tmp2);
> + gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
> rd = 16;
> break;
> case 0xb: /* cmn */
> - gen_helper_add_cc(tmp, tmp, tmp2);
> + gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
> rd = 16;
> break;
> case 0xc: /* orr */
> @@ -9913,7 +9913,7 @@ static inline void
> gen_intermediate_code_internal(CPUARMState *env,
> /* nothing more to generate */
> break;
> case DISAS_WFI:
> - gen_helper_wfi();
> + gen_helper_wfi(cpu_env);
> break;
> case DISAS_SWI:
> gen_exception(EXCP_SWI);
> --
> 1.7.2.5
>
- [Qemu-devel] [PATCH 06/21] target-s390x: rename op_helper.c to misc_helper.c, (continued)
- [Qemu-devel] [PATCH 06/21] target-s390x: rename op_helper.c to misc_helper.c, Blue Swirl, 2012/09/02
- [Qemu-devel] [PATCH 05/21] target-s390x: split memory access helpers, Blue Swirl, 2012/09/02
- [Qemu-devel] [PATCH 08/21] target-s390x: avoid AREG0 for integer helpers, Blue Swirl, 2012/09/02
- [Qemu-devel] [PATCH 07/21] target-s390x: avoid AREG0 for FPU helpers, Blue Swirl, 2012/09/02
- [Qemu-devel] [PATCH 09/21] target-s390x: avoid AREG0 for condition code helpers, Blue Swirl, 2012/09/02
- [Qemu-devel] [PATCH 10/21] target-s390x: avoid AREG0 for misc helpers, Blue Swirl, 2012/09/02
- [Qemu-devel] [PATCH 12/21] target-s390x: split helper.c, Blue Swirl, 2012/09/02
- [Qemu-devel] [PATCH 14/21] target-m68k: switch to AREG0 free mode, Blue Swirl, 2012/09/02
- [Qemu-devel] [PATCH 16/21] target-arm: switch to AREG0 free mode, Blue Swirl, 2012/09/02
- Re: [Qemu-devel] [PATCH 16/21] target-arm: switch to AREG0 free mode,
Peter Maydell <=
- Re: [Qemu-devel] [PATCH 16/21] target-arm: switch to AREG0 free mode, Peter Maydell, 2012/09/02
- Re: [Qemu-devel] [PATCH 16/21] target-arm: switch to AREG0 free mode, Blue Swirl, 2012/09/03
- Re: [Qemu-devel] [PATCH 16/21] target-arm: switch to AREG0 free mode, Peter Maydell, 2012/09/03
- Re: [Qemu-devel] [PATCH 16/21] target-arm: switch to AREG0 free mode, Blue Swirl, 2012/09/03
- Re: [Qemu-devel] [PATCH 16/21] target-arm: switch to AREG0 free mode, Peter Maydell, 2012/09/03
Re: [Qemu-devel] [PATCH 16/21] target-arm: switch to AREG0 free mode, Peter Maydell, 2012/09/03
[Qemu-devel] [PATCH 17/21] target-microblaze: switch to AREG0 free mode, Blue Swirl, 2012/09/02
[Qemu-devel] [PATCH 18/21] target-cris: switch to AREG0 free mode, Blue Swirl, 2012/09/02