[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH 12/14] target-mips: use deposit instead of hardcoded
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [PATCH 12/14] target-mips: use deposit instead of hardcoded version |
Date: |
Tue, 9 Oct 2012 22:27:36 +0200 |
Use the deposit op instead of and hardcoded bit field insertion. It
allows the host to emit the corresponding instruction if available.
Signed-off-by: Aurelien Jarno <address@hidden>
---
target-mips/translate.c | 27 ++++-----------------------
1 file changed, 4 insertions(+), 23 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 7d87f66..d996fd2 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -3406,7 +3406,6 @@ static void gen_bitops (DisasContext *ctx, uint32_t opc,
int rt,
{
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
- target_ulong mask;
gen_load_gpr(t1, rs);
switch (opc) {
@@ -3439,45 +3438,27 @@ static void gen_bitops (DisasContext *ctx, uint32_t
opc, int rt,
case OPC_INS:
if (lsb > msb)
goto fail;
- mask = ((msb - lsb + 1 < 32) ? ((1 << (msb - lsb + 1)) - 1) : ~0) <<
lsb;
gen_load_gpr(t0, rt);
- tcg_gen_andi_tl(t0, t0, ~mask);
- tcg_gen_shli_tl(t1, t1, lsb);
- tcg_gen_andi_tl(t1, t1, mask);
- tcg_gen_or_tl(t0, t0, t1);
+ tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1);
tcg_gen_ext32s_tl(t0, t0);
break;
#if defined(TARGET_MIPS64)
case OPC_DINSM:
if (lsb > msb)
goto fail;
- mask = ((msb - lsb + 1 + 32 < 64) ? ((1ULL << (msb - lsb + 1 + 32)) -
1) : ~0ULL) << lsb;
- gen_load_gpr(t0, rt);
- tcg_gen_andi_tl(t0, t0, ~mask);
- tcg_gen_shli_tl(t1, t1, lsb);
- tcg_gen_andi_tl(t1, t1, mask);
- tcg_gen_or_tl(t0, t0, t1);
+ tcg_gen_deposit_tl(t0, t0, t1, lsb, msb + 32 - lsb + 1);
break;
case OPC_DINSU:
if (lsb > msb)
goto fail;
- mask = ((1ULL << (msb - lsb + 1)) - 1) << (lsb + 32);
gen_load_gpr(t0, rt);
- tcg_gen_andi_tl(t0, t0, ~mask);
- tcg_gen_shli_tl(t1, t1, lsb + 32);
- tcg_gen_andi_tl(t1, t1, mask);
- tcg_gen_or_tl(t0, t0, t1);
+ tcg_gen_deposit_tl(t0, t0, t1, lsb + 32, msb - lsb + 1);
break;
case OPC_DINS:
if (lsb > msb)
goto fail;
gen_load_gpr(t0, rt);
- mask = ((1ULL << (msb - lsb + 1)) - 1) << lsb;
- gen_load_gpr(t0, rt);
- tcg_gen_andi_tl(t0, t0, ~mask);
- tcg_gen_shli_tl(t1, t1, lsb);
- tcg_gen_andi_tl(t1, t1, mask);
- tcg_gen_or_tl(t0, t0, t1);
+ tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1);
break;
#endif
default:
--
1.7.10.4
- [Qemu-devel] [PATCH 00/14] target-mips: misc fixes and optimizations, Aurelien Jarno, 2012/10/09
- [Qemu-devel] [PATCH 09/14] target-mips: don't use local temps for store conditional, Aurelien Jarno, 2012/10/09
- [Qemu-devel] [PATCH 07/14] target-mips: simplify load/store microMIPS helpers, Aurelien Jarno, 2012/10/09
- [Qemu-devel] [PATCH 01/14] softfloat: implement fused multiply-add NaN propagation for MIPS, Aurelien Jarno, 2012/10/09
- [Qemu-devel] [PATCH 03/14] target-mips: fix FPU exceptions, Aurelien Jarno, 2012/10/09
- [Qemu-devel] [PATCH 14/14] target-mips: don't flush extra TLB on permissions upgrade, Aurelien Jarno, 2012/10/09
- [Qemu-devel] [PATCH 12/14] target-mips: use deposit instead of hardcoded version,
Aurelien Jarno <=
- [Qemu-devel] [PATCH 13/14] target-mips: fix TLBR wrt SEGMask, Aurelien Jarno, 2012/10/09
- [Qemu-devel] [PATCH 04/14] target-mips: use softfloat constants when possible, Aurelien Jarno, 2012/10/09
- [Qemu-devel] [PATCH 05/14] target-mips: cleanup load/store operations, Aurelien Jarno, 2012/10/09
- [Qemu-devel] [PATCH 11/14] target-mips: optimize ddiv/ddivu/div/divu with movcond, Aurelien Jarno, 2012/10/09