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[Qemu-devel] [PATCH 19/20] target-sparc: Make cpu_dst local to OP=2 insn
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 19/20] target-sparc: Make cpu_dst local to OP=2 insns |
Date: |
Tue, 9 Oct 2012 15:04:26 -0700 |
And initialize it such that it (may) write directly to rd.
Signed-off-by: Richard Henderson <address@hidden>
---
target-sparc/translate.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 5b7e82b..8559cc3 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -48,7 +48,7 @@ static TCGv cpu_y;
#ifndef CONFIG_USER_ONLY
static TCGv cpu_tbr;
#endif
-static TCGv cpu_cond, cpu_dst;
+static TCGv cpu_cond;
#ifdef TARGET_SPARC64
static TCGv_i32 cpu_xcc, cpu_asi, cpu_fprs;
static TCGv cpu_gsr;
@@ -2511,7 +2511,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned
int insn)
}
opc = GET_FIELD(insn, 0, 1);
-
rd = GET_FIELD(insn, 2, 6);
switch (opc) {
@@ -2620,6 +2619,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned
int insn)
case 2: /* FPU & Logical Operations */
{
unsigned int xop = GET_FIELD(insn, 7, 12);
+ TCGv cpu_dst = gen_dest_gpr(dc, rd);
+
if (xop == 0x3a) { /* generate trap */
int cond = GET_FIELD(insn, 3, 6);
TCGv_i32 trap;
@@ -5258,12 +5259,10 @@ static inline void
gen_intermediate_code_internal(TranslationBlock * tb,
insn = cpu_ldl_code(env, dc->pc);
cpu_tmp0 = tcg_temp_new();
- cpu_dst = tcg_temp_new();
disas_sparc_insn(dc, insn);
num_insns++;
- tcg_temp_free(cpu_dst);
tcg_temp_free(cpu_tmp0);
if (dc->is_br)
--
1.7.11.4
- [Qemu-devel] [PATCH 09/20] target-sparc: Split out get_temp_i32, (continued)
- [Qemu-devel] [PATCH 09/20] target-sparc: Split out get_temp_i32, Richard Henderson, 2012/10/09
- [Qemu-devel] [PATCH 12/20] target-sparc: Avoid cpu_tmp32 in Write Priv Register, Richard Henderson, 2012/10/09
- [Qemu-devel] [PATCH 10/20] target-sparc: Use get_temp_i32 in gen_dest_fpr_F, Richard Henderson, 2012/10/09
- [Qemu-devel] [PATCH 11/20] target-sparc: Avoid cpu_tmp32 in Read Priv Register, Richard Henderson, 2012/10/09
- [Qemu-devel] [PATCH 08/20] target-sparc: Make the cpu_addr variable local to load/store handling, Richard Henderson, 2012/10/09
- [Qemu-devel] [PATCH 13/20] target-sparc: Tidy ldfsr, stfsr, Richard Henderson, 2012/10/09
- [Qemu-devel] [PATCH 16/20] target-sparc: Remove cpu_tmp64 use from softint insns, Richard Henderson, 2012/10/09
- [Qemu-devel] [PATCH 15/20] target-sparc: Don't use a temporary for gen_dest_fpr_D, Richard Henderson, 2012/10/09
- [Qemu-devel] [PATCH 14/20] target-sparc: Remove usage of cpu_tmp64 from most helper functions, Richard Henderson, 2012/10/09
- [Qemu-devel] [PATCH 17/20] target-sparc: Remove last uses of cpu_tmp64, Richard Henderson, 2012/10/09
- [Qemu-devel] [PATCH 19/20] target-sparc: Make cpu_dst local to OP=2 insns,
Richard Henderson <=
- [Qemu-devel] [PATCH 20/20] target-sparc: Remove cpu_tmp0 as a global, Richard Henderson, 2012/10/09
- [Qemu-devel] [PATCH 18/20] target-sparc: Only use cpu_dst for eventual writes to a gpr, Richard Henderson, 2012/10/09
- Re: [Qemu-devel] [PATCH 00/20] target-sparc: Cleanup handling of temps, Blue Swirl, 2012/10/13