Re: [Qemu-devel] [PATCH] mips/malta: fix CBUS UART interrupt pin

[Johnson, Eric]

> -----Original Message-----
> From: address@hidden [mailto:qemu-devel-
> address@hidden On Behalf Of Aurelien Jarno
> Sent: Wednesday, November 14, 2012 6:38 AM
> To: address@hidden
> Cc: Aurelien Jarno
> Subject: [Qemu-devel] [PATCH] mips/malta: fix CBUS UART interrupt pin
> 
> According to the MIPS Malta Developement Platform User's Manual, the
> i8259 interrupt controller is supposed to be connected to the hardware
> IRQ0, and the CBUS UART to the hardware interrupt 2.
> 
> In QEMU they are both connected to hardware interrupt 0, the CBUS UART
> interrupt being wrong. This patch fixes that. It should be noted that
> the irq array in QEMU includes the software interrupts, hence
> env->irq[2] is the first hardware interrupt.
> 
> Cc: Ralf Baechle <address@hidden>
> Signed-off-by: Aurelien Jarno <address@hidden>
> ---
>  hw/mips_malta.c |    3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/mips_malta.c b/hw/mips_malta.c
> index 0571d58..4d2464a 100644
> --- a/hw/mips_malta.c
> +++ b/hw/mips_malta.c
> @@ -861,7 +861,8 @@ void mips_malta_init(QEMUMachineInitArgs *args)
>      be = 0;
>  #endif
>      /* FPGA */
> -    malta_fpga_init(system_memory, FPGA_ADDRESS, env->irq[2],
> serial_hds[2]);
> +    /* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4
> */
> +    malta_fpga_init(system_memory, FPGA_ADDRESS, env->irq[4],
> serial_hds[2]);
> 
>      /* Load firmware in flash / BIOS. */
>      dinfo = drive_get(IF_PFLASH, 0, fl_idx);
> --
> 1.7.10.4
> 

I double checked with a Malta expert here.  He verified that the CBUS UART is 
connected to the HW2 interrupt pin.

Reviewed-by: Eric Johnson <address@hidden>

-Eric