On 16.01.2013, at 18:23, Marcelo Tosatti wrote:
> What register is that and why it cannot be synced normally? When is
it
> necessary to sync it?
We need to sync it on the above 2 occasions.
Thinking about this a bit more, we're trying to keep the
synchronization window short to not get into conflicts with the
kernel timer kicking in in between. Imagine this race:
* user space reads TSR
* kernel timer expires, sets bit in TSR
* user space writes TSR
That's why we don't want this to be synced every time. We would only
set TSR when we reset the counter. At that point in time it doesn't
hurt to lose the kernel timer set, because we cleared the bit anyways.
But maybe the better solution would be a special "write to clear"
ONE_REG register to clear specific bits and a big hammer "set"
ONE_REG (which we have already) for reset only.
That would make things easier, right? Scott, any ideas on this?