[Qemu-devel] [PATCH 18/19] hw: remove CPU dependencies

[Paolo Bonzini]

Some devices or headers are using poisoned identifiers.
For .c files, some are useless and we remove them.

For headers, wrap the definitions in the headers with

Signed-off-by: Paolo Bonzini <address@hidden>
---
 hw/char/etraxfs_ser.c        |    2 --
 hw/char/sclpconsole.c        |    2 +-
 hw/display/exynos4210_fimd.c |    1 -
 hw/pci/host-apb.c            |    8 ++++----
 include/hw/arm/exynos4210.h  |   10 +++++++---
 include/hw/arm/omap.h        |    4 ++++
 include/hw/arm/pxa.h         |   12 ++++++++++--
 include/hw/cris/etraxfs.h    |    2 ++
 include/hw/m68k/mcf.h        |    4 ++++
 include/hw/misc/pcmcia.h     |    1 +
 include/hw/pci/q35.h         |    1 -
 include/hw/ppc/ppc.h         |    6 ++++++
 include/hw/ppc/ppc4xx.h      |   13 +++++++------
 include/hw/sh4/sh.h          |    2 ++
 include/hw/sparc/sun4m.h     |    2 ++
 15 files changed, 50 insertions(+), 20 deletions(-)

diff --git a/hw/char/etraxfs_ser.c b/hw/char/etraxfs_ser.c
index 7e24d34..b7499d7 100644
--- a/hw/char/etraxfs_ser.c
+++ b/hw/char/etraxfs_ser.c
@@ -78,7 +78,6 @@ static uint64_t
 ser_read(void *opaque, hwaddr addr, unsigned int size)
 {
     struct etrax_serial *s = opaque;
-    D(CPUCRISState *env = s->env);
     uint32_t r = 0;
 
     addr >>= 2;
@@ -116,7 +115,6 @@ ser_write(void *opaque, hwaddr addr,
     struct etrax_serial *s = opaque;
     uint32_t value = val64;
     unsigned char ch = val64;
-    D(CPUCRISState *env = s->env);
 
     D(qemu_log("%s " TARGET_FMT_plx "=%x\n",  __func__, addr, value));
     addr >>= 2;
diff --git a/hw/char/sclpconsole.c b/hw/char/sclpconsole.c
index 01ee76b..673db04 100644
--- a/hw/char/sclpconsole.c
+++ b/hw/char/sclpconsole.c
@@ -237,7 +237,7 @@ static int write_event_data(SCLPEvent *event, 
EventBufferHeader *evt_buf_hdr)
     return rc;
 }
 
-static void trigger_ascii_console_data(void *env, int n, int level)
+static void trigger_ascii_console_data(void *s, int n, int level)
 {
     sclp_service_interrupt(0);
 }
diff --git a/hw/display/exynos4210_fimd.c b/hw/display/exynos4210_fimd.c
index 501dc5c..0c7aef9 100644
--- a/hw/display/exynos4210_fimd.c
+++ b/hw/display/exynos4210_fimd.c
@@ -23,7 +23,6 @@
  */
 
 #include "qemu-common.h"
-#include "exec/cpu-all.h"
 #include "hw/sysbus.h"
 #include "ui/console.h"
 #include "ui/pixel_ops.h"
diff --git a/hw/pci/host-apb.c b/hw/pci/host-apb.c
index 672a9fc..c7004d1 100644
--- a/hw/pci/host-apb.c
+++ b/hw/pci/host-apb.c
@@ -92,7 +92,7 @@ static void apb_config_writel (void *opaque, hwaddr addr,
 {
     APBState *s = opaque;
 
-    APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %" PRIx64 "\n", __func__, 
addr, val);
+    APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__, 
addr, val);
 
     switch (addr & 0xffff) {
     case 0x30 ... 0x4f: /* DMA error registers */
@@ -201,7 +201,7 @@ static uint64_t apb_config_readl (void *opaque,
         val = 0;
         break;
     }
-    APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, val);
+    APB_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, val);
 
     return val;
 }
@@ -218,7 +218,7 @@ static void apb_pci_config_write(void *opaque, hwaddr addr,
     APBState *s = opaque;
 
     val = qemu_bswap_len(val, size);
-    APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %" PRIx64 "\n", __func__, 
addr, val);
+    APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__, 
addr, val);
     pci_data_write(s->bus, addr, val, size);
 }
 
@@ -230,7 +230,7 @@ static uint64_t apb_pci_config_read(void *opaque, hwaddr 
addr,
 
     ret = pci_data_read(s->bus, addr, size);
     ret = qemu_bswap_len(ret, size);
-    APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, ret);
+    APB_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, ret);
     return ret;
 }
 
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index bb9a1dd..8798cbe 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -84,7 +84,10 @@ typedef struct Exynos4210Irq {
     qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
 } Exynos4210Irq;
 
-typedef struct Exynos4210State {
+typedef struct Exynos4210State Exynos4210State;
+
+#ifdef NEED_CPU_H
+struct Exynos4210State {
     ARMCPU *cpu[EXYNOS4210_NCPUS];
     Exynos4210Irq irqs;
     qemu_irq *irq_table;
@@ -98,16 +101,17 @@ typedef struct Exynos4210State {
     MemoryRegion boot_secondary;
     MemoryRegion bootreg_mem;
     i2c_bus *i2c_if[EXYNOS4210_I2C_NUMBER];
-} Exynos4210State;
+};
 
 void exynos4210_write_secondary(ARMCPU *cpu,
         const struct arm_boot_info *info);
+#endif
 
 Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
         unsigned long ram_size);
 
 /* Initialize exynos4210 IRQ subsystem stub */
-qemu_irq *exynos4210_init_irq(Exynos4210Irq *env);
+qemu_irq *exynos4210_init_irq(Exynos4210Irq *s);
 
 /* Initialize board IRQs.
  * These IRQs contain splitted Int/External Combiner and External Gic IRQs */
diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h
index 188cda8..c53e717 100644
--- a/include/hw/arm/omap.h
+++ b/include/hw/arm/omap.h
@@ -790,6 +790,9 @@ i2c_bus *omap_i2c_bus(DeviceState *omap_i2c);
 # define cpu_class_omap3(cpu) \
         (cpu_is_omap3430(cpu) || cpu_is_omap3630(cpu))
 
+struct omap_mpu_state_s;
+
+#ifdef NEED_CPU_H
 struct omap_mpu_state_s {
     enum omap_mpu_model {
         omap310,
@@ -932,6 +935,7 @@ struct omap_mpu_state_s {
 
     struct omap_eac_s *eac;
 };
+#endif
 
 /* omap1.c */
 struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
diff --git a/include/hw/arm/pxa.h b/include/hw/arm/pxa.h
index 668232c..eccd4b7 100644
--- a/include/hw/arm/pxa.h
+++ b/include/hw/arm/pxa.h
@@ -65,11 +65,16 @@
 # define PXA2XX_INTERNAL_SIZE  0x40000
 
 /* pxa2xx_pic.c */
+#ifdef NEED_CPU_H
 DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu);
+#endif
 
 /* pxa2xx_gpio.c */
+#ifdef NEED_CPU_H
 DeviceState *pxa2xx_gpio_init(hwaddr base,
                               ARMCPU *cpu, DeviceState *pic, int lines);
+#endif
+
 void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler);
 
 /* pxa2xx_dma.c */
@@ -121,7 +126,9 @@ i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s);
 typedef struct PXA2xxI2SState PXA2xxI2SState;
 typedef struct PXA2xxFIrState PXA2xxFIrState;
 
-typedef struct {
+typedef struct PXA2xxState PXA2xxState;
+#ifdef NEED_CPU_H
+struct PXA2xxState {
     ARMCPU *cpu;
     DeviceState *pic;
     qemu_irq reset;
@@ -156,7 +163,8 @@ typedef struct {
 
     /* Performance monitoring */
     uint32_t pmnc;
-} PXA2xxState;
+};
+#endif
 
 struct PXA2xxI2SState {
     MemoryRegion iomem;
diff --git a/include/hw/cris/etraxfs.h b/include/hw/cris/etraxfs.h
index ab30559..3c4d5a3 100644
--- a/include/hw/cris/etraxfs.h
+++ b/include/hw/cris/etraxfs.h
@@ -28,7 +28,9 @@
 #include "net/net.h"
 #include "hw/cris/etraxfs_dma.h"
 
+#ifdef NEED_CPU_H
 qemu_irq *cris_pic_init_cpu(CPUCRISState *env);
+#endif
 
 /* Instantiate an ETRAXFS Ethernet MAC.  */
 static inline DeviceState *
diff --git a/include/hw/m68k/mcf.h b/include/hw/m68k/mcf.h
index f929910..28903e7 100644
--- a/include/hw/m68k/mcf.h
+++ b/include/hw/m68k/mcf.h
@@ -15,16 +15,20 @@ void mcf_uart_mm_init(struct MemoryRegion *sysmem,
                       qemu_irq irq, CharDriverState *chr);
 
 /* mcf_intc.c */
+#ifdef NEED_CPU_H
 qemu_irq *mcf_intc_init(struct MemoryRegion *sysmem,
                         hwaddr base,
                         CPUM68KState *env);
+#endif
 
 /* mcf_fec.c */
 void mcf_fec_init(struct MemoryRegion *sysmem, NICInfo *nd,
                   hwaddr base, qemu_irq *irq);
 
 /* mcf5206.c */
+#ifdef NEED_CPU_H
 qemu_irq *mcf5206_init(struct MemoryRegion *sysmem,
                        uint32_t base, CPUM68KState *env);
+#endif
 
 #endif
diff --git a/include/hw/misc/pcmcia.h b/include/hw/misc/pcmcia.h
index f916693..e70cfa3 100644
--- a/include/hw/misc/pcmcia.h
+++ b/include/hw/misc/pcmcia.h
@@ -4,6 +4,7 @@
 /* PCMCIA/Cardbus */
 
 #include "qemu-common.h"
+#include "monitor/monitor.h"
 
 typedef struct {
     qemu_irq irq;
diff --git a/include/hw/pci/q35.h b/include/hw/pci/q35.h
index 5e27e5d..542fc85 100644
--- a/include/hw/pci/q35.h
+++ b/include/hw/pci/q35.h
@@ -28,7 +28,6 @@
 #include "hw/sysbus.h"
 #include "hw/pc.h"
 #include "hw/isa/apm.h"
-#include "hw/i386/apic.h"
 #include "hw/pci/pci.h"
 #include "hw/pci/pcie_host.h"
 #include "hw/acpi/acpi.h"
diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h
index ee0cd16..c11e684 100644
--- a/include/hw/ppc/ppc.h
+++ b/include/hw/ppc/ppc.h
@@ -1,7 +1,9 @@
 #ifndef HW_PPC_H
 #define HW_PPC_H 1
 
+#ifdef NEED_CPU_H
 void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level);
+#endif
 
 /* PowerPC hardware exceptions management helpers */
 typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
@@ -45,6 +47,7 @@ struct ppc_tb_t {
                                                * the decrementer reaches zero.
                                                */
 
+#ifdef NEED_CPU_H
 uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset);
 clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq);
 /* Embedded PowerPC DCR management */
@@ -72,6 +75,7 @@ void ppce500_irq_init (CPUPPCState *env);
 void ppc6xx_irq_init (CPUPPCState *env);
 void ppc970_irq_init (CPUPPCState *env);
 void ppcPOWER7_irq_init (CPUPPCState *env);
+#endif
 
 void ppce500_set_mpic_proxy(bool enabled);
 
@@ -94,6 +98,8 @@ enum {
 #define PPC_SERIAL_MM_BAUDBASE 399193
 
 /* ppc_booke.c */
+#ifdef NEED_CPU_H
 void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags);
+#endif
 
 #endif
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index 91d84ba..d75dd0b 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -28,9 +28,11 @@
 #include "hw/pci/pci.h"
 
 /* PowerPC 4xx core initialization */
+#ifdef NEED_CPU_H
 PowerPCCPU *ppc4xx_init(const char *cpu_model,
                         clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
                         uint32_t sysclk);
+#endif
 
 /* PowerPC 4xx universal interrupt controller */
 enum {
@@ -38,8 +40,11 @@ enum {
     PPCUIC_OUTPUT_CINT = 1,
     PPCUIC_OUTPUT_NB,
 };
+
+#ifdef NEED_CPU_H
 qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs,
                        uint32_t dcr_base, int has_ssr, int has_vr);
+#endif
 
 ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
                                MemoryRegion ram_memories[],
@@ -47,18 +52,14 @@ ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int 
nr_banks,
                                hwaddr ram_sizes[],
                                const unsigned int sdram_bank_sizes[]);
 
+#ifdef NEED_CPU_H
 void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
                         MemoryRegion ram_memories[],
                         hwaddr *ram_bases,
                         hwaddr *ram_sizes,
                         int do_init);
+#endif
 
 #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
 
-PCIBus *ppc4xx_pci_init(CPUPPCState *env, qemu_irq pci_irqs[4],
-                        hwaddr config_space,
-                        hwaddr int_ack,
-                        hwaddr special_cycle,
-                        hwaddr registers);
-
 #endif /* !defined(PPC_4XX_H) */
diff --git a/include/hw/sh4/sh.h b/include/hw/sh4/sh.h
index 87c378f..dcfb4ac 100644
--- a/include/hw/sh4/sh.h
+++ b/include/hw/sh4/sh.h
@@ -11,7 +11,9 @@
 struct SH7750State;
 struct MemoryRegion;
 
+#ifdef NEED_CPU_H
 struct SH7750State *sh7750_init(CPUSH4State * cpu, struct MemoryRegion 
*sysmem);
+#endif
 
 typedef struct {
     /* The callback will be triggered if any of the designated lines change */
diff --git a/include/hw/sparc/sun4m.h b/include/hw/sparc/sun4m.h
index e984671..d92ca4b 100644
--- a/include/hw/sparc/sun4m.h
+++ b/include/hw/sparc/sun4m.h
@@ -2,6 +2,8 @@
 #define SUN4M_H
 
 #include "qemu-common.h"
+#include "exec/hwaddr.h"
+#include "monitor/monitor.h"
 
 /* Devices used by sparc32 system.  */
 
-- 
1.7.4.1