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[Qemu-devel] [PATCH 24/38] target-ppc: Use mul*2 in mulh* insns
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 24/38] target-ppc: Use mul*2 in mulh* insns |
Date: |
Tue, 19 Feb 2013 23:52:12 -0800 |
Cc: Alexander Graf <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target-ppc/helper.h | 2 --
target-ppc/int_helper.c | 18 -----------
target-ppc/translate.c | 82 +++++++++++++++++++++++--------------------------
3 files changed, 38 insertions(+), 64 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 18e0394..fcf372a 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -30,8 +30,6 @@ DEF_HELPER_2(icbi, void, env, tl)
DEF_HELPER_5(lscbx, tl, env, tl, i32, i32, i32)
#if defined(TARGET_PPC64)
-DEF_HELPER_FLAGS_2(mulhd, TCG_CALL_NO_RWG_SE, i64, i64, i64)
-DEF_HELPER_FLAGS_2(mulhdu, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_3(mulldo, i64, env, i64, i64)
#endif
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 783079d..8653151 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -25,24 +25,6 @@
/* Fixed point operations helpers */
#if defined(TARGET_PPC64)
-/* multiply high word */
-uint64_t helper_mulhd(uint64_t arg1, uint64_t arg2)
-{
- uint64_t tl, th;
-
- muls64(&tl, &th, arg1, arg2);
- return th;
-}
-
-/* multiply high word unsigned */
-uint64_t helper_mulhdu(uint64_t arg1, uint64_t arg2)
-{
- uint64_t tl, th;
-
- mulu64(&tl, &th, arg1, arg2);
- return th;
-}
-
uint64_t helper_mulldo(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
{
int64_t th;
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 2ac5794..2673a89 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1061,24 +1061,15 @@ GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
/* mulhw mulhw. */
static void gen_mulhw(DisasContext *ctx)
{
- TCGv_i64 t0, t1;
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ TCGv_i32 t1 = tcg_temp_new_i32();
- t0 = tcg_temp_new_i64();
- t1 = tcg_temp_new_i64();
-#if defined(TARGET_PPC64)
- tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
- tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
- tcg_gen_mul_i64(t0, t0, t1);
- tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
-#else
- tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
- tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
- tcg_gen_mul_i64(t0, t0, t1);
- tcg_gen_shri_i64(t0, t0, 32);
- tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
-#endif
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(t1);
+ tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
+ tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
+ tcg_gen_muls2_i32(t0, t1, t0, t1);
+ tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
+ tcg_temp_free_i32(t0);
+ tcg_temp_free_i32(t1);
if (unlikely(Rc(ctx->opcode) != 0))
gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
}
@@ -1086,24 +1077,15 @@ static void gen_mulhw(DisasContext *ctx)
/* mulhwu mulhwu. */
static void gen_mulhwu(DisasContext *ctx)
{
- TCGv_i64 t0, t1;
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ TCGv_i32 t1 = tcg_temp_new_i32();
- t0 = tcg_temp_new_i64();
- t1 = tcg_temp_new_i64();
-#if defined(TARGET_PPC64)
- tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
- tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
- tcg_gen_mul_i64(t0, t0, t1);
- tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
-#else
- tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
- tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
- tcg_gen_mul_i64(t0, t0, t1);
- tcg_gen_shri_i64(t0, t0, 32);
- tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
-#endif
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(t1);
+ tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
+ tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
+ tcg_gen_mulu2_i32(t0, t1, t0, t1);
+ tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
+ tcg_temp_free_i32(t0);
+ tcg_temp_free_i32(t1);
if (unlikely(Rc(ctx->opcode) != 0))
gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
}
@@ -1159,19 +1141,31 @@ static void gen_mulli(DisasContext *ctx)
tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
SIMM(ctx->opcode));
}
+
#if defined(TARGET_PPC64)
-#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
-static void glue(gen_, name)(DisasContext *ctx)
\
-{ \
- gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
- cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
- if (unlikely(Rc(ctx->opcode) != 0)) \
- gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
-}
/* mulhd mulhd. */
-GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
+static void gen_mulhd(DisasContext *ctx)
+{
+ TCGv lo = tcg_temp_new();
+ tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
+ cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
+ tcg_temp_free(lo);
+ if (unlikely(Rc(ctx->opcode) != 0)) {
+ gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
+ }
+}
+
/* mulhdu mulhdu. */
-GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
+static void gen_mulhdu(DisasContext *ctx)
+{
+ TCGv lo = tcg_temp_new();
+ tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
+ cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
+ tcg_temp_free(lo);
+ if (unlikely(Rc(ctx->opcode) != 0)) {
+ gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
+ }
+}
/* mulld mulld. */
static void gen_mulld(DisasContext *ctx)
--
1.8.1.2
- [Qemu-devel] [PATCH 13/38] tcg: Implement muls2 with mulu2, (continued)
- [Qemu-devel] [PATCH 13/38] tcg: Implement muls2 with mulu2, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 18/38] target-arm: Use mul[us]2 and add2 in umlal et al, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 15/38] target-alpha: Use mulu2 for umulh insn, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 28/38] target-ppc: Compute addition carry with setcond, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 32/38] target-ppc: Compute mullwo without branches, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 34/38] target-sparc: Use mul*2 for multiply, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 33/38] target-sparc: Use official add2/sub2 interfaces for addx/subx, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 30/38] target-ppc: Implement neg in terms of subf, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 36/38] target-unicore32: Use mul*2 for do_mult, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 24/38] target-ppc: Use mul*2 in mulh* insns,
Richard Henderson <=
- [Qemu-devel] [PATCH 20/38] target-arm: Implement adc_cc inline, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 37/38] target-xtensa: Use mul*2 for mul*hi, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 35/38] target-sh4: Use mul*2 for dmul*, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 31/38] target-ppc: Compute arithmetic shift carry without branches, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 29/38] target-ppc: Use add2 for carry generation, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 19/38] target-arm: Use add2 in gen_add_CC, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 27/38] target-ppc: Compute addition overflow without branches, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 22/38] target-mips: Use mul[us]2 in [D]MULT[U] insns, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 23/38] target-cris: Use mul*2 in mul* insns, Richard Henderson, 2013/02/20