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[Qemu-devel] [PATCH 26/38] target-ppc: Use setcond in gen_op_cmp
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 26/38] target-ppc: Use setcond in gen_op_cmp |
Date: |
Tue, 19 Feb 2013 23:52:14 -0800 |
Which means that callers need not copy data into local tmps.
Cc: Alexander Graf <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target-ppc/translate.c | 46 +++++++++++++++++++++++-----------------------
1 file changed, 23 insertions(+), 23 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 0ac072c..7aab6ae 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -596,33 +596,33 @@ static opc_handler_t invalid_handler = {
static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
{
- int l1, l2, l3;
+ TCGv t0 = tcg_temp_new();
+ TCGv_i32 t1 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
- l1 = gen_new_label();
- l2 = gen_new_label();
- l3 = gen_new_label();
- if (s) {
- tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
- tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
- } else {
- tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
- tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
- }
- tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
- tcg_gen_br(l3);
- gen_set_label(l1);
- tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
- tcg_gen_br(l3);
- gen_set_label(l2);
- tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
- gen_set_label(l3);
+ tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
+ tcg_gen_trunc_tl_i32(t1, t0);
+ tcg_gen_shli_i32(t1, t1, CRF_LT);
+ tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
+
+ tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
+ tcg_gen_trunc_tl_i32(t1, t0);
+ tcg_gen_shli_i32(t1, t1, CRF_GT);
+ tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
+
+ tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
+ tcg_gen_trunc_tl_i32(t1, t0);
+ tcg_gen_shli_i32(t1, t1, CRF_EQ);
+ tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free_i32(t1);
}
static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
{
- TCGv t0 = tcg_const_local_tl(arg1);
+ TCGv t0 = tcg_const_tl(arg1);
gen_op_cmp(arg0, t0, s, crf);
tcg_temp_free(t0);
}
@@ -631,8 +631,8 @@ static inline void gen_op_cmpi(TCGv arg0, target_ulong
arg1, int s, int crf)
static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
{
TCGv t0, t1;
- t0 = tcg_temp_local_new();
- t1 = tcg_temp_local_new();
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
if (s) {
tcg_gen_ext32s_tl(t0, arg0);
tcg_gen_ext32s_tl(t1, arg1);
@@ -647,7 +647,7 @@ static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int
s, int crf)
static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
{
- TCGv t0 = tcg_const_local_tl(arg1);
+ TCGv t0 = tcg_const_tl(arg1);
gen_op_cmp32(arg0, t0, s, crf);
tcg_temp_free(t0);
}
--
1.8.1.2
- [Qemu-devel] [PATCH 35/38] target-sh4: Use mul*2 for dmul*, (continued)
- [Qemu-devel] [PATCH 35/38] target-sh4: Use mul*2 for dmul*, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 31/38] target-ppc: Compute arithmetic shift carry without branches, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 29/38] target-ppc: Use add2 for carry generation, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 19/38] target-arm: Use add2 in gen_add_CC, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 27/38] target-ppc: Compute addition overflow without branches, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 22/38] target-mips: Use mul[us]2 in [D]MULT[U] insns, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 23/38] target-cris: Use mul*2 in mul* insns, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 25/38] target-ppc: Split out SO, OV, CA fields from XER, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 17/38] target-arm: Use mul[us]2 in gen_mul[us]_i64_i32, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 38/38] target-xtensa: Use add2/sub2 for mac, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 26/38] target-ppc: Use setcond in gen_op_cmp,
Richard Henderson <=
- [Qemu-devel] [PATCH 21/38] target-arm: Implement sbc_cc inline, Richard Henderson, 2013/02/20
- Re: [Qemu-devel] [PATCH 00/38] Add double-word addition and widening multiply tcg ops, Blue Swirl, 2013/02/23
- Re: [Qemu-devel] [PATCH 00/38] Add double-word addition and widening multiply tcg ops, Alexander Graf, 2013/02/25