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[Qemu-devel] [PATCH 4/4] target-arm: always set endian bits in big-endia


From: Fabien Chouteau
Subject: [Qemu-devel] [PATCH 4/4] target-arm: always set endian bits in big-endian mode
Date: Fri, 1 Mar 2013 18:21:47 +0100

CPSR.E, SCTLR.EE and SCTLR.IE

Signed-off-by: Fabien Chouteau <address@hidden>
---
 target-arm/cpu.c    |   11 +++++++++++
 target-arm/helper.c |   18 ++++++++++++++++++
 2 files changed, 29 insertions(+)

diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 5dfcb74..354843e 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -112,6 +112,17 @@ static void arm_cpu_reset(CPUState *s)
     }
     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 #endif
+
+#ifdef TARGET_WORDS_BIGENDIAN
+    if (arm_feature(env, ARM_FEATURE_V6) || arm_feature(env, ARM_FEATURE_V7)) {
+        /* Set IE and EE bits for big-endian */
+        env->cp15.c1_sys |= (1 << 31) | (1 << 25);
+
+        /* Set E bit for big-endian */
+        env->uncached_cpsr |= CPSR_E;
+    }
+#endif
+
     set_flush_to_zero(1, &env->vfp.standard_fp_status);
     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
     set_default_nan_mode(1, &env->vfp.standard_fp_status);
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 75ee0dc..e539186 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1017,6 +1017,15 @@ static const ARMCPRegInfo lpae_cp_reginfo[] = {
 static int sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t 
value)
 {
     env->cp15.c1_sys = value;
+
+#ifdef TARGET_WORDS_BIGENDIAN
+    if (arm_feature(env, ARM_FEATURE_V6)
+        || arm_feature(env, ARM_FEATURE_V7)) {
+        /* IE and EE bits stay set for big-endian */
+        env->cp15.c1_sys |= (1 << 31) | (1 << 25);
+    }
+#endif
+
     /* ??? Lots of these bits are not implemented.  */
     /* This may enable/disable the MMU, so do a TLB flush.  */
     tlb_flush(env, 1);
@@ -1509,6 +1518,15 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t 
mask)
     }
     mask &= ~CACHED_CPSR_BITS;
     env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
+
+#ifdef TARGET_WORDS_BIGENDIAN
+    if (arm_feature(env, ARM_FEATURE_V6)
+        || arm_feature(env, ARM_FEATURE_V7)) {
+        /* E bit stays set for big-endian */
+        env->uncached_cpsr |= CPSR_E;
+    }
+#endif
+
 }
 
 /* Sign/zero extend */
-- 
1.7.9.5




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