Re: [Qemu-devel] Cortex-M4F Floating Point system registers

[Peter Maydell]

On 20 March 2013 16:05, Fabien Chouteau <address@hidden> wrote:
> I'm looking at the ARMv7-M profile and the implementation in QEMU.
> Looks like M3 is supported and I'd like to work on M4F (FP context save
> and lazy FP context save).

This is going to be interesting because we don't currently have
any mechanisms implemented for 'trap on attempt to use FP insn'.
(Not impossible, just the code isn't there at the moment.)

> I wonder how the FPU system registers, and more generally how the
> co-processor registers are implemented in QEMU.
>
> For example in the Cortex-M4 TRM it seems like FP system registers are
> mapped in memory. I don't see that implemented in QEMU.

Yes, M profile maps lots of sysregs in memory. Mostly we implement
these in hw/armv7m_nvic.c. It's kind of ugly the way that code
reaches into the CPU implementation though.

-- PMM