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[Qemu-devel] [PATCH v4 22/33] tcg-ppc64: Handle constant inputs for some
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v4 22/33] tcg-ppc64: Handle constant inputs for some compound logicals |
Date: |
Thu, 4 Apr 2013 17:56:15 -0500 |
Since we have special code to handle and/or/xor with a constant,
apply the same to andc/orc/eqv with a constant.
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/ppc64/tcg-target.c | 44 ++++++++++++++++++++++++++++++++++----------
1 file changed, 34 insertions(+), 10 deletions(-)
diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index 89832e5..7c326c5 100644
--- a/tcg/ppc64/tcg-target.c
+++ b/tcg/ppc64/tcg-target.c
@@ -1394,17 +1394,19 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc,
const TCGArg *args,
break;
case INDEX_op_and_i32:
+ a0 = args[0], a1 = args[1], a2 = args[2];
if (const_args[2]) {
- tcg_out_andi32(s, args[0], args[1], args[2]);
+ tcg_out_andi32(s, a0, a1, a2);
} else {
- tcg_out32(s, AND | SAB(args[1], args[0], args[2]));
+ tcg_out32(s, AND | SAB(a1, a0, a2));
}
break;
case INDEX_op_and_i64:
+ a0 = args[0], a1 = args[1], a2 = args[2];
if (const_args[2]) {
- tcg_out_andi64(s, args[0], args[1], args[2]);
+ tcg_out_andi64(s, a0, a1, a2);
} else {
- tcg_out32(s, AND | SAB(args[1], args[0], args[2]));
+ tcg_out32(s, AND | SAB(a1, a0, a2));
}
break;
case INDEX_op_or_i64:
@@ -1426,14 +1428,36 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc,
const TCGArg *args,
}
break;
case INDEX_op_andc_i32:
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ if (const_args[2]) {
+ tcg_out_andi32(s, a0, a1, ~a2);
+ } else {
+ tcg_out32(s, ANDC | SAB(a1, a0, a2));
+ }
+ break;
case INDEX_op_andc_i64:
- tcg_out32(s, ANDC | SAB(args[1], args[0], args[2]));
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ if (const_args[2]) {
+ tcg_out_andi64(s, a0, a1, ~a2);
+ } else {
+ tcg_out32(s, ANDC | SAB(a1, a0, a2));
+ }
break;
case INDEX_op_orc_i32:
+ if (const_args[2]) {
+ tcg_out_ori32(s, args[0], args[1], ~args[2]);
+ break;
+ }
+ /* FALLTHRU */
case INDEX_op_orc_i64:
tcg_out32(s, ORC | SAB(args[1], args[0], args[2]));
break;
case INDEX_op_eqv_i32:
+ if (const_args[2]) {
+ tcg_out_xori32(s, args[0], args[1], ~args[2]);
+ break;
+ }
+ /* FALLTHRU */
case INDEX_op_eqv_i64:
tcg_out32(s, EQV | SAB(args[1], args[0], args[2]));
break;
@@ -1820,9 +1844,9 @@ static const TCGTargetOpDef ppc_op_defs[] = {
{ INDEX_op_and_i32, { "r", "r", "ri" } },
{ INDEX_op_or_i32, { "r", "r", "ri" } },
{ INDEX_op_xor_i32, { "r", "r", "ri" } },
- { INDEX_op_andc_i32, { "r", "r", "r" } },
- { INDEX_op_orc_i32, { "r", "r", "r" } },
- { INDEX_op_eqv_i32, { "r", "r", "r" } },
+ { INDEX_op_andc_i32, { "r", "r", "ri" } },
+ { INDEX_op_orc_i32, { "r", "r", "ri" } },
+ { INDEX_op_eqv_i32, { "r", "r", "ri" } },
{ INDEX_op_nand_i32, { "r", "r", "r" } },
{ INDEX_op_nor_i32, { "r", "r", "r" } },
@@ -1840,10 +1864,10 @@ static const TCGTargetOpDef ppc_op_defs[] = {
{ INDEX_op_add_i64, { "r", "r", "rT" } },
{ INDEX_op_sub_i64, { "r", "rI", "rT" } },
- { INDEX_op_and_i64, { "r", "r", "rU" } },
+ { INDEX_op_and_i64, { "r", "r", "ri" } },
{ INDEX_op_or_i64, { "r", "r", "rU" } },
{ INDEX_op_xor_i64, { "r", "r", "rU" } },
- { INDEX_op_andc_i64, { "r", "r", "r" } },
+ { INDEX_op_andc_i64, { "r", "r", "ri" } },
{ INDEX_op_orc_i64, { "r", "r", "r" } },
{ INDEX_op_eqv_i64, { "r", "r", "r" } },
{ INDEX_op_nand_i64, { "r", "r", "r" } },
--
1.8.1.4
- [Qemu-devel] [PATCH v4 16/33] tcg-ppc64: Use automatic implementation of ext32u_i64, (continued)
- [Qemu-devel] [PATCH v4 16/33] tcg-ppc64: Use automatic implementation of ext32u_i64, Richard Henderson, 2013/04/04
- [Qemu-devel] [PATCH v4 17/33] tcg-ppc64: Streamline qemu_ld/st insn selection, Richard Henderson, 2013/04/04
- [Qemu-devel] [PATCH v4 19/33] tcg-ppc64: Implement bswap16 and bswap32, Richard Henderson, 2013/04/04
- [Qemu-devel] [PATCH v4 18/33] tcg-ppc64: Implement rotates, Richard Henderson, 2013/04/04
- [Qemu-devel] [PATCH v4 20/33] tcg-ppc64: Implement bswap64, Richard Henderson, 2013/04/04
- [Qemu-devel] [PATCH v4 21/33] tcg-ppc64: Implement compound logicals, Richard Henderson, 2013/04/04
- [Qemu-devel] [PATCH v4 23/33] tcg-ppc64: Implement deposit, Richard Henderson, 2013/04/04
- [Qemu-devel] [PATCH v4 22/33] tcg-ppc64: Handle constant inputs for some compound logicals,
Richard Henderson <=
- [Qemu-devel] [PATCH v4 24/33] tcg-ppc64: Use I constraint for mul, Richard Henderson, 2013/04/04
- [Qemu-devel] [PATCH v4 25/33] tcg-ppc64: Cleanup i32 constants to tcg_out_cmp, Richard Henderson, 2013/04/04
- [Qemu-devel] [PATCH v4 26/33] tcg-ppc64: Use TCGType throughout compares, Richard Henderson, 2013/04/04
- [Qemu-devel] [PATCH v4 27/33] tcg-ppc64: Use MFOCRF instead of MFCR, Richard Henderson, 2013/04/04
- [Qemu-devel] [PATCH v4 28/33] tcg-ppc64: Use ISEL for setcond, Richard Henderson, 2013/04/04
- [Qemu-devel] [PATCH v4 30/33] tcg-ppc64: Use getauxval for ISA detection, Richard Henderson, 2013/04/04