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Re: [Qemu-devel] [PATCH arm-devs v1 11/15] xilinx_spips: Fix striping be
From: |
Peter Crosthwaite |
Subject: |
Re: [Qemu-devel] [PATCH arm-devs v1 11/15] xilinx_spips: Fix striping behaviour |
Date: |
Mon, 8 Apr 2013 18:21:26 +1000 |
Hi Peter,
On Sat, Apr 6, 2013 at 4:59 AM, Peter Maydell <address@hidden> wrote:
> On 3 April 2013 05:33, Peter Crosthwaite <address@hidden> wrote:
>> The QSPI controller was using byte-wide stripes when striping across
>> the two flashes in dual parallel mode. The real hardware however uses
>> individual bit striping. QEMU misbehaves in the (corner) case where
>> data is written/read in dual-parallel mode and read/written back in
>> single mode.
>>
>> Signed-off-by: Peter Crosthwaite <address@hidden>
>> ---
>>
>> hw/xilinx_spips.c | 74
>> ++++++++++++++++++++++++++++++++++++++---------------
>> 1 files changed, 53 insertions(+), 21 deletions(-)
>>
>> diff --git a/hw/xilinx_spips.c b/hw/xilinx_spips.c
>> index a2019e4..43ce2d8 100644
>> --- a/hw/xilinx_spips.c
>> +++ b/hw/xilinx_spips.c
>> @@ -258,35 +258,67 @@ static void xilinx_spips_reset(DeviceState *d)
>> xilinx_spips_update_cs_lines(s);
>> }
>>
>> +static inline void stripe8(uint8_t *x, int num, bool dir)
>> +{
>> + uint8_t r[num];
>> + memset(r, 0, sizeof(uint8_t) * num);
>
> Don't interleave code and variable definitions, please.
>
>> + int idx[2] = {0, 0};
>> + int bit[2] = {0, 0};
>> + int d = dir;
>> +
>> + for (idx[0] = 0; idx[0] < num; ++idx[0]) {
>> + for (bit[0] = 0; bit[0] < 8; ++bit[0]) {
>> + r[idx[d]] |= x[idx[!d]] & 1 << bit[!d] ? 1 << bit[d] : 0;
>> + idx[1] = (idx[1] + 1) % num;
>> + if (!idx[1]) {
>> + bit[1]++;
>> + }
>> + }
>> + }
>> + memcpy(x, r, sizeof(uint8_t) * num);
>> +}
>
> This function could really use a comment saying what it's doing...
>
+/* N way (num) in place bit striper. Lay out row wise bits (LSB to MSB)
+ * column wise (from element 0 to N-1). num is the length of x, and dir
+ * reverses the direction of the transform. Best illustrated by example:
+ * Each digit in the below array is a single bit (num == 3):
+ *
+ * {{ 76543210, } ----- stripe (dir == false) -----> {{ FCheb630, }
+ * { hgfedcba, } { GDAfc741, }
+ * { HGFEDCBA, }} <---- upstripe (dir == true) ----- { HEBgda52, }}
+ */
+
Regards,
Peter
>
> thanks
> -- PMM
>
- Re: [Qemu-devel] [PATCH arm-devs v1 06/15] xilinx_spips: Fix QSPI FIFO size, (continued)
- [Qemu-devel] [PATCH arm-devs v1 07/15] xilinx_spips: Trash LQ page cache on mode change, Peter Crosthwaite, 2013/04/03
- [Qemu-devel] [PATCH arm-devs v1 08/15] xilinx_spips: Add automatic start support, Peter Crosthwaite, 2013/04/03
- [Qemu-devel] [PATCH arm-devs v1 09/15] xilinx_spips: Implement automatic CS, Peter Crosthwaite, 2013/04/03
- [Qemu-devel] [PATCH arm-devs v1 10/15] xilinx_spips: Fix CTRL register RW bits, Peter Crosthwaite, 2013/04/03
- [Qemu-devel] [PATCH arm-devs v1 11/15] xilinx_spips: Fix striping behaviour, Peter Crosthwaite, 2013/04/03
- [Qemu-devel] [PATCH arm-devs v1 12/15] xilinx_spips: Debug msgs for Snoop state, Peter Crosthwaite, 2013/04/03
- [Qemu-devel] [PATCH arm-devs v1 13/15] xilinx_spips: Multiple debug verbosity levels, Peter Crosthwaite, 2013/04/03
- [Qemu-devel] [PATCH arm-devs v1 14/15] xilinx_spips: lqspi: Push more data to tx-fifo, Peter Crosthwaite, 2013/04/03
- [Qemu-devel] [PATCH arm-devs v1 15/15] xilinx_spips: lqspi: Fix byte/misaligned access, Peter Crosthwaite, 2013/04/03