Re: [Qemu-devel] [PATCH v4 08/33] tcg-ppc64: Fix setcond_i32

[Aurelien Jarno]

On Thu, Apr 04, 2013 at 05:56:01PM -0500, Richard Henderson wrote:
> We weren't ignoring the high 32 bits during a NE comparison.
> 
> Signed-off-by: Richard Henderson <address@hidden>
> ---
>  tcg/ppc64/tcg-target.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
> index b12cbec..822eb07 100644
> --- a/tcg/ppc64/tcg-target.c
> +++ b/tcg/ppc64/tcg-target.c
> @@ -1129,6 +1129,12 @@ static void tcg_out_setcond (TCGContext *s, TCGType 
> type, TCGCond cond,
>              tcg_out32 (s, XOR | SAB (arg1, 0, arg2));
>          }
>  
> +        /* Make sure and discard the high 32-bits of the input.  */
> +        if (type == TCG_TYPE_I32) {
> +            tcg_out32(s, EXTSW | RA(TCG_REG_R0) | RS(arg));
> +            arg = TCG_REG_R0;
> +        }
> +
>          if (arg == arg1 && arg1 == arg0) {
>              tcg_out32(s, ADDIC | TAI(0, arg, -1));
>              tcg_out32(s, SUBFE | TAB(arg0, 0, arg));

Given that it adds one more instruction, I do wonder if we still need a
different implementation than the EQ one and XORI 1. The latter is what
GCC choses.

That said the fix is correct so:

Reviewed-by: Aurelien Jarno <address@hidden>

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
address@hidden                 http://www.aurel32.net