[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH v5 19/33] tcg-ppc64: Implement bswap16 and bswap
From: |
Aurelien Jarno |
Subject: |
Re: [Qemu-devel] [PATCH v5 19/33] tcg-ppc64: Implement bswap16 and bswap32 |
Date: |
Mon, 15 Apr 2013 22:04:02 +0200 |
User-agent: |
Mutt/1.5.21 (2010-09-15) |
On Mon, Apr 15, 2013 at 08:40:58PM +0200, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <address@hidden>
> ---
> tcg/ppc64/tcg-target.c | 43 +++++++++++++++++++++++++++++++++++++++++++
> tcg/ppc64/tcg-target.h | 8 ++++----
> 2 files changed, 47 insertions(+), 4 deletions(-)
>
> diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
> index 18338a2..1c6be96 100644
> --- a/tcg/ppc64/tcg-target.c
> +++ b/tcg/ppc64/tcg-target.c
> @@ -1676,6 +1676,44 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc,
> const TCGArg *args,
> const_args[2]);
> break;
>
> + case INDEX_op_bswap16_i32:
> + case INDEX_op_bswap16_i64:
> + a0 = args[0], a1 = args[1];
> + /* a1 = abcd */
> + if (a0 != a1) {
> + /* a0 = (a1 r<< 24) & 0xff # 000c */
> + tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
> + /* a0 = (a0 & ~0xff00) | (a1 r<< 8) & 0xff00 # 00dc */
> + tcg_out_rlw(s, RLWIMI, a0, a1, 8, 16, 23);
> + } else {
> + /* r0 = (a1 r<< 8) & 0xff00 # 00d0 */
> + tcg_out_rlw(s, RLWINM, TCG_REG_R0, a1, 8, 16, 23);
> + /* a0 = (a1 r<< 24) & 0xff # 000c */
> + tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
> + /* a0 = a0 | r0 # 00dc */
> + tcg_out32(s, OR | SAB(TCG_REG_R0, a0, a0));
> + }
> + break;
> +
> + case INDEX_op_bswap32_i32:
> + case INDEX_op_bswap32_i64:
> + /* Stolen from gcc's builtin_bswap32 */
> + a1 = args[1];
> + a0 = args[0] == a1 ? TCG_REG_R0 : args[0];
> +
> + /* a1 = args[1] # abcd */
> + /* a0 = rotate_left (a1, 8) # bcda */
> + tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
> + /* a0 = (a0 & ~0xff000000) | ((a1 r<< 24) & 0xff000000) # dcda */
> + tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
> + /* a0 = (a0 & ~0x0000ff00) | ((a1 r<< 24) & 0x0000ff00) # dcba */
> + tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
> +
> + if (a0 == TCG_REG_R0) {
> + tcg_out_mov(s, TCG_TYPE_I64, args[0], a0);
> + }
> + break;
> +
> default:
> tcg_dump_ops (s);
> tcg_abort ();
> @@ -1781,6 +1819,11 @@ static const TCGTargetOpDef ppc_op_defs[] = {
> { INDEX_op_setcond_i32, { "r", "r", "ri" } },
> { INDEX_op_setcond_i64, { "r", "r", "ri" } },
>
> + { INDEX_op_bswap16_i32, { "r", "r" } },
> + { INDEX_op_bswap16_i64, { "r", "r" } },
> + { INDEX_op_bswap32_i32, { "r", "r" } },
> + { INDEX_op_bswap32_i64, { "r", "r" } },
> +
> { -1 },
> };
>
> diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h
> index b2713a0..7cd1e98 100644
> --- a/tcg/ppc64/tcg-target.h
> +++ b/tcg/ppc64/tcg-target.h
> @@ -79,8 +79,8 @@ typedef enum {
> #define TCG_TARGET_HAS_rot_i32 1
> #define TCG_TARGET_HAS_ext8s_i32 1
> #define TCG_TARGET_HAS_ext16s_i32 1
> -#define TCG_TARGET_HAS_bswap16_i32 0
> -#define TCG_TARGET_HAS_bswap32_i32 0
> +#define TCG_TARGET_HAS_bswap16_i32 1
> +#define TCG_TARGET_HAS_bswap32_i32 1
> #define TCG_TARGET_HAS_not_i32 1
> #define TCG_TARGET_HAS_neg_i32 1
> #define TCG_TARGET_HAS_andc_i32 0
> @@ -100,8 +100,8 @@ typedef enum {
> #define TCG_TARGET_HAS_ext8s_i64 1
> #define TCG_TARGET_HAS_ext16s_i64 1
> #define TCG_TARGET_HAS_ext32s_i64 1
> -#define TCG_TARGET_HAS_bswap16_i64 0
> -#define TCG_TARGET_HAS_bswap32_i64 0
> +#define TCG_TARGET_HAS_bswap16_i64 1
> +#define TCG_TARGET_HAS_bswap32_i64 1
> #define TCG_TARGET_HAS_bswap64_i64 0
> #define TCG_TARGET_HAS_not_i64 1
> #define TCG_TARGET_HAS_neg_i64 1
Thanks for changing this one:
Signed-off-by: Richard Henderson <address@hidden>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
address@hidden http://www.aurel32.net
- [Qemu-devel] [PATCH v5 10/33] tcg-ppc64: Rearrange integer constant constraints, (continued)
- [Qemu-devel] [PATCH v5 10/33] tcg-ppc64: Rearrange integer constant constraints, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 11/33] tcg-ppc64: Improve constant add and sub ops., Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 12/33] tcg-ppc64: Allow constant first argument to sub, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 13/33] tcg-ppc64: Tidy or and xor patterns., Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 14/33] tcg-ppc64: Improve and_i32 with constant, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 15/33] tcg-ppc64: Improve and_i64 with constant, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 16/33] tcg-ppc64: Use automatic implementation of ext32u_i64, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 17/33] tcg-ppc64: Streamline qemu_ld/st insn selection, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 18/33] tcg-ppc64: Implement rotates, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 19/33] tcg-ppc64: Implement bswap16 and bswap32, Richard Henderson, 2013/04/15
- Re: [Qemu-devel] [PATCH v5 19/33] tcg-ppc64: Implement bswap16 and bswap32,
Aurelien Jarno <=
- [Qemu-devel] [PATCH v5 20/33] tcg-ppc64: Implement bswap64, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 22/33] tcg-ppc64: Handle constant inputs for some compound logicals, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 23/33] tcg-ppc64: Implement deposit, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 24/33] tcg-ppc64: Use I constraint for mul, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 25/33] tcg-ppc64: Use TCGType throughout compares, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 26/33] tcg-ppc64: Cleanup i32 constants to tcg_out_cmp, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 27/33] tcg-ppc64: Use MFOCRF instead of MFCR, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 28/33] tcg-ppc64: Use ISEL for setcond, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 30/33] tcg-ppc64: Use getauxval for ISA detection, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 31/33] tcg-ppc64: Implement add2/sub2_i64, Richard Henderson, 2013/04/15