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Re: [Qemu-devel] [PATCH 09/10] target-ppc: emulate store doubleword pair


From: Aurelien Jarno
Subject: Re: [Qemu-devel] [PATCH 09/10] target-ppc: emulate store doubleword pair instructions
Date: Fri, 19 Apr 2013 20:54:12 +0200
User-agent: Mutt/1.5.20 (2009-06-14)

On Wed, Apr 17, 2013 at 04:26:44PM +0200, Richard Henderson wrote:
> On 2013-04-13 14:47, Aurelien Jarno wrote:
> >+        gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
> 
> Actually, for both this and ldfp, don't you need to check for
> odd rD and raise sigill or whatever?
> 

This indeed needs to be checked, but it's already done using the invalid
bits:
+GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
+GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),

The 2 there correspond to the last bit of the register pair, which thus
should be 0, otherwise the instruction generates an invalid exception.

I'll add that to the description when doing the respin.

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
address@hidden                 http://www.aurel32.net



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