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[Qemu-devel] [PATCH arm-devs v2 2/5] sd/sdhci: Fix Buffer Write Ready in
From: |
peter . crosthwaite |
Subject: |
[Qemu-devel] [PATCH arm-devs v2 2/5] sd/sdhci: Fix Buffer Write Ready interrupt |
Date: |
Fri, 24 May 2013 15:16:00 +1000 |
From: Peter Crosthwaite <address@hidden>
This interrupt is not risen after the last block is written to sd. It
is mutually exclusive with the end of transfer conditions. Fix.
Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Igor Mitsyanko <address@hidden>
---
hw/sd/sdhci.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 0a84540..ea510b5 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -405,15 +405,14 @@ static void sdhci_write_block_to_card(SDHCIState *s)
/* Next data can be written through BUFFER DATORT register */
s->prnsts |= SDHC_SPACE_AVAILABLE;
- if (s->norintstsen & SDHC_NISEN_WBUFRDY) {
- s->norintsts |= SDHC_NIS_WBUFRDY;
- }
/* Finish transfer if that was the last block of data */
if ((s->trnmod & SDHC_TRNS_MULTI) == 0 ||
((s->trnmod & SDHC_TRNS_MULTI) &&
(s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0))) {
SDHCI_GET_CLASS(s)->end_data_transfer(s);
+ } else if (s->norintstsen & SDHC_NISEN_WBUFRDY) {
+ s->norintsts |= SDHC_NIS_WBUFRDY;
}
/* Generate Block Gap Event if requested and if not the last block */
--
1.8.3.rc1.44.gb387c77.dirty
- [Qemu-devel] [PATCH arm-devs v2 0/5] SD and SDHCI Fixes, peter . crosthwaite, 2013/05/24
- [Qemu-devel] [PATCH arm-devs v2 1/5] sd/sdhci.c: Only reset data_count on new commands, peter . crosthwaite, 2013/05/24
- [Qemu-devel] [PATCH arm-devs v2 2/5] sd/sdhci: Fix Buffer Write Ready interrupt,
peter . crosthwaite <=
- [Qemu-devel] [PATCH arm-devs v2 3/5] sd/sdhci.c: Fix bdata_read DPRINT message, peter . crosthwaite, 2013/05/24
- [Qemu-devel] [PATCH arm-devs v2 4/5] sd/sdhci:ADMA: fix interrupt, peter . crosthwaite, 2013/05/24
- [Qemu-devel] [PATCH arm-devs v2 5/5] sd/sd.c: Fix "inquiry" ACMD41, peter . crosthwaite, 2013/05/24
- Re: [Qemu-devel] [PATCH arm-devs v2 0/5] SD and SDHCI Fixes, Peter Maydell, 2013/05/24