[Qemu-devel] [PATCH] target-mips: 64-bit FPU for user-mode emulation.

[Thomas Schwinge]

Switch to 64-bit FPU only for n32 and n64 ABIs, but not o32.  Fixup for
commit 68473f15d4c9948986618f63828825beafcaf1cf.

Signed-off-by: Thomas Schwinge <address@hidden>

---

Hi!

On Sun, 10 Feb 2013 10:30:46 -0800, Richard Henderson <address@hidden> wrote:
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index 3b77b53..b3b8dc6 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -15972,6 +15972,14 @@ void cpu_state_reset(CPUMIPSState *env)
>  
>  #if defined(CONFIG_USER_ONLY)
>      env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU);
> +# ifdef TARGET_MIPS64
> +    /* Enable 64-bit register mode.  */
> +    env->CP0_Status |= (1 << CP0St_PX);
> +# endif
> +# ifdef TARGET_ABI_MIPSN64
> +    /* Enable 64-bit address mode.  */
> +    env->CP0_Status |= (1 << CP0St_UX);
> +# endif
>      /* Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR
>         hardware registers.  */
>      env->CP0_HWREna |= 0x0000000F;
> @@ -15981,6 +15989,11 @@ void cpu_state_reset(CPUMIPSState *env)
>      if (env->CP0_Config3 & (1 << CP0C3_DSPP)) {
>          env->CP0_Status |= (1 << CP0St_MX);
>      }
> +    /* Enable 64-bit FPU if the target cpu supports it.  */
> +    env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0;
> +    if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
> +        env->CP0_Status |= (1 << CP0St_FR);
> +    }
>  #else
>      if (env->hflags & MIPS_HFLAG_BMASK) {
>          /* If the exception was raised from a delay slot,

In my reading of the relevant documents, the latter change is not correct
for o32, and empirically has "interesting" effects on the glibc math
testsuite, for example.  Keeping the FR register unset for o32 I'm
proposing to fix with the following patch:

---
 target-mips/translate.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git target-mips/translate.c target-mips/translate.c
index 0a53203..51837d4 100644
--- target-mips/translate.c
+++ target-mips/translate.c
@@ -15962,10 +15962,12 @@ void cpu_state_reset(CPUMIPSState *env)
     if (env->CP0_Config3 & (1 << CP0C3_DSPP)) {
         env->CP0_Status |= (1 << CP0St_MX);
     }
-    /* Enable 64-bit FPU if the target cpu supports it.  */
+# if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
+    /* Enable 64-bit FPU if the target CPU supports it.  */
     if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
         env->CP0_Status |= (1 << CP0St_FR);
     }
+# endif
 #else
     if (env->hflags & MIPS_HFLAG_BMASK) {
         /* If the exception was raised from a delay slot,


Grüße,
 Thomas

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