[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 07/13] tcg/aarch64: implement AND/TEST immediate patt
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 07/13] tcg/aarch64: implement AND/TEST immediate pattern |
Date: |
Wed, 12 Jun 2013 16:57:19 +0100 |
From: Claudio Fontana <address@hidden>
add functions to AND/TEST registers with immediate patterns.
Signed-off-by: Claudio Fontana <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
tcg/aarch64/tcg-target.c | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 2aa9f75..bb59794 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -580,6 +580,40 @@ static inline void tcg_out_call(TCGContext *s,
tcg_target_long target)
}
}
+/* encode a logical immediate, mapping user parameter
+ M=set bits pattern length to S=M-1 */
+static inline unsigned int
+aarch64_limm(unsigned int m, unsigned int r)
+{
+ assert(m > 0);
+ return r << 16 | (m - 1) << 10;
+}
+
+/* test a register against an immediate bit pattern made of
+ M set bits rotated right by R.
+ Examples:
+ to test a 32/64 reg against 0x00000007, pass M = 3, R = 0.
+ to test a 32/64 reg against 0x000000ff, pass M = 8, R = 0.
+ to test a 32bit reg against 0xff000000, pass M = 8, R = 8.
+ to test a 32bit reg against 0xff0000ff, pass M = 16, R = 8.
+ */
+static inline void tcg_out_tst(TCGContext *s, int ext, TCGReg rn,
+ unsigned int m, unsigned int r)
+{
+ /* using TST alias of ANDS XZR, Xn,#bimm64 0x7200001f */
+ unsigned int base = ext ? 0xf240001f : 0x7200001f;
+ tcg_out32(s, base | aarch64_limm(m, r) | rn << 5);
+}
+
+/* and a register with a bit pattern, similarly to TST, no flags change */
+static inline void tcg_out_andi(TCGContext *s, int ext, TCGReg rd, TCGReg rn,
+ unsigned int m, unsigned int r)
+{
+ /* using AND 0x12000000 */
+ unsigned int base = ext ? 0x92400000 : 0x12000000;
+ tcg_out32(s, base | aarch64_limm(m, r) | rn << 5 | rd);
+}
+
static inline void tcg_out_ret(TCGContext *s)
{
/* emit RET { LR } */
--
1.7.9.5
- [Qemu-devel] [PULL 00/13] tcg-aarch64 queue, Peter Maydell, 2013/06/12
- [Qemu-devel] [PULL 02/13] linux-user: Drop direct use of openat etc syscalls, Peter Maydell, 2013/06/12
- [Qemu-devel] [PULL 10/13] user-exec.c: aarch64 initial implementation of cpu_signal_handler, Peter Maydell, 2013/06/12
- [Qemu-devel] [PULL 03/13] configure: Drop CONFIG_ATFILE test, Peter Maydell, 2013/06/12
- [Qemu-devel] [PULL 12/13] configure: permit compilation on arm aarch64, Peter Maydell, 2013/06/12
- [Qemu-devel] [PULL 01/13] linux-user: Allow getdents to be provided by getdents64, Peter Maydell, 2013/06/12
- [Qemu-devel] [PULL 07/13] tcg/aarch64: implement AND/TEST immediate pattern,
Peter Maydell <=
- [Qemu-devel] [PULL 04/13] include/elf.h: add aarch64 ELF machine and relocs, Peter Maydell, 2013/06/12
- [Qemu-devel] [PULL 13/13] MAINTAINERS: add tcg/aarch64 maintainer, Peter Maydell, 2013/06/12
- [Qemu-devel] [PULL 05/13] tcg/aarch64: implement new TCG target for aarch64, Peter Maydell, 2013/06/12
- [Qemu-devel] [PULL 11/13] tcg/aarch64: implement user mode qemu ld/st, Peter Maydell, 2013/06/12
- [Qemu-devel] [PULL 06/13] tcg/aarch64: improve arith shifted regs operations, Peter Maydell, 2013/06/12
- [Qemu-devel] [PULL 08/13] tcg/aarch64: implement byte swap operations, Peter Maydell, 2013/06/12
- [Qemu-devel] [PULL 09/13] tcg/aarch64: implement sign/zero extend operations, Peter Maydell, 2013/06/12
- Re: [Qemu-devel] [PULL 00/13] tcg-aarch64 queue, Anthony Liguori, 2013/06/17